Merge "ARM: dts: msm: Add GPU support for sdm429w"

#include "sdm429-cpu.dtsi"

#include "sdm429-cpu.dtsi"

#include "sdm429-ion.dtsi"

#include "sdm429-ion.dtsi"

#include "msm-arm-smmu-sdm429.dtsi"

#include "msm-arm-smmu-sdm429.dtsi"

#include "sdm429w-gpu.dtsi"

&soc {

&soc {

	#address-cells = <1>;

	#address-cells = <1>;

	#size-cells = <1>;

	#size-cells = <1>;

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

&soc {

	msm_bus: qcom,kgsl-busmon {

		label = "kgsl-busmon";

		compatible = "qcom,kgsl-busmon";

	};

	gpubw: qcom,gpubw {

		compatible = "qcom,devbw";

		governor = "bw_vbif";

		qcom,src-dst-ports = <26 512>;

		/*

		 * active-only flag is used while registering the bus

		 * governor.It helps release the bus vote when the CPU

		 * subsystem is inactive

		 */

		 qcom,active-only;

		 qcom,bw-tbl =

			<    0 >, /*  off */

			<  769 >, /* 1. DDR:100.80 MHz BIMC: 50.40 MHz */

			< 1611 >, /* 2. DDR:211.20 MHz BIMC: 105.60 MHz */

			< 2273 >, /* 3. DDR:297.60 MHz BIMC: 148.80 MHz */

			< 2929 >, /* 4. DDR:384.00 MHz BIMC: 192.00 MHz */

			< 4248 >, /* 5. DDR:556.80 MHz BIMC: 278.40 MHz */

			< 5346 >, /* 6. DDR:662.40 MHz BIMC: 331.20 MHz */

			< 5712 >, /* 7. DDR:748.80 MHz BIMC: 374.40 MHz */

			< 6150 >, /* 8. DDR:796.80 MHz BIMC: 398.40 MHz */

			< 7105 >; /* 9. DDR:931.20 MHz BIMC: 465.60 MHz */

	};

	msm_gpu: qcom,kgsl-3d0@1c00000 {

		label = "kgsl-3d0";

		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";

		status = "ok";

		reg = <0x1c00000 0x40000

			  0xa0000 0x6fff>;

		reg-names = "kgsl_3d0_reg_memory", "qfprom_memory";

		interrupts = <0 33 0>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;

		qcom,chipid = <0x05000400>;

		qcom,initial-pwrlevel = <0>;

		qcom,idle-timeout = <80>; //msecs

		qcom,strtstp-sleepwake;

		qcom,highest-bank-bit = <14>;

		qcom,snapshot-size = <1048576>; //bytes

		clocks = <&gcc GCC_OXILI_GFX3D_CLK>,

				 <&gcc GCC_OXILI_AHB_CLK>,

				 <&gcc GCC_BIMC_GFX_CLK>,

				 <&gcc GCC_BIMC_GPU_CLK>,

				 <&gcc GCC_OXILI_TIMER_CLK>,

				 <&gcc GCC_OXILI_AON_CLK>;

		clock-names = "core_clk", "iface_clk",

				"mem_iface_clk", "alt_mem_iface_clk",

				"rbbmtimer_clk", "alwayson_clk";

		/* Bus Scale Settings */

		qcom,gpubw-dev = <&gpubw>;

		qcom,bus-control;

		qcom,bus-width = <16>;

		qcom,msm-bus,name = "grp3d";

		qcom,msm-bus,num-cases = <10>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<26 512 0 0>,       /*    off        */

			<26 512 0 806400>, /* 1. 100.80 MHz */

			<26 512 0 1689600>, /* 2. 211.20 MHz */

			<26 512 0 2380800>, /* 3. 297.60 MHz */

			<26 512 0 3072000>, /* 4. 384.00 MHz */

			<26 512 0 4454400>, /* 5. 556.80 MHz */

			<26 512 0 5299200>, /* 6. 662.40 MHz */

			<26 512 0 5990400>, /* 7. 748.80 MHz */

			<26 512 0 6374400>, /* 8. 796.80 MHz */

			<26 512 0 7449600>; /* 9. 931.20 MHz */

		/* GDSC regulator names */

		regulator-names = "vddcx", "vdd";

		/* GDSC oxili regulators */

		vddcx-supply = <&oxili_cx_gdsc>;

		vdd-supply = <&oxili_gx_gdsc>;

		/* CPU latency parameter */

		qcom,pm-qos-active-latency = <360>;

		qcom,pm-qos-wakeup-latency = <360>;

		/*  Quirks  */

		qcom,gpu-quirk-two-pass-use-wfi;

		qcom,gpu-quirk-dp2clockgating-disable;

		qcom,gpu-quirk-lmloadkill-disable;

		/* Enable context aware freq. scaling */

		qcom,enable-ca-jump;

		/* Context aware jump busy penalty in us */

		qcom,ca-busy-penalty = <12000>;

		/* Context aware jump target power level */

		qcom,ca-target-pwrlevel = <1>;

		/* Enable gpu cooling device */

		#cooling-cells = <2>;

		/* Power levels */

		qcom,gpu-pwrlevels {

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <320000000>;

				qcom,bus-freq = <2>;

				qcom,bus-min = <2>;

				qcom,bus-max = <2>;

			};

			qcom,gpu-pwrlevel@1{

				reg = <1>;

				qcom,gpu-freq = <19200000>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};

	};

	kgsl_msm_iommu: qcom,kgsl-iommu@1c40000 {

		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x1c40000 0x10000>;

		qcom,protect = <0x40000 0x10000>;

		qcom,micro-mmu-control = <0x6000>;

		clocks = <&gcc GCC_OXILI_AHB_CLK>,

			 <&gcc GCC_BIMC_GFX_CLK>;

		clock-names = "gpu_ahb_clk", "gcc_bimc_gfx_clk";

		qcom,secure_align_mask = <0xfff>;

		qcom,retention;

		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_user";

			iommus = <&kgsl_smmu 0>;

			qcom,gpu-offset = <0x48000>;

		};

	};

};