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Commit ead882ef authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add SPM control for sdm429w"

parents be1c2aa9 9231d59e

Documentation/devicetree/bindings/clock/qcom,sdm-cpucc.txt

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Qualcomm Technologies, Inc. SDM CPU clock driver

---------------------------------------------------



It is the clock controller driver which provides higher frequency

clocks and allows CPU frequency scaling on sdm based platforms.



Required properties:

- compatible:	Shall contain following:

		"qcom,cpu-clock-sdm"

- clocks:	Phandle to the clock device.

- clock-names:	Names of the used clocks. Shall contain following:

		"xo_ao", "gpll0_ao"

- reg:	Shall contain base register offset and size.

- reg-names:	Names of the bases for the above registers. Shall contain following:

		"apcs-c1-rcg-base", "apcs-cci-rcg-base", "apcs_pll", "efuse"

- vdd_dig_ao-supply:	The regulator(active only) powering the digital logic of APSS PLL.

- vdd_hf_pll-supply:	The regulator(active only) powering the Analog logic of APSS PLL.

- cpu-vdd-supply:	The regulator powering the APSS C1 RCG and APSS CCI RCG.

- qcom,speedX-bin-vY-Z:	A table of CPU frequency (Hz) to regulator voltage (uV) mapping.

			Format: <freq uV>

			This represents the max frequency possible for each possible

			power configuration for a CPU that's binned as speed bin X,

			speed bin revision Y. Version can be between [0-3]. Z

			is the mux id c1 or cci.

- #clock-cells:	Shall contain 1.



Example:

	clock_cpu: qcom,clock-cpu@0b011050 {

		compatible = "qcom,cpu-clock-sdm";

		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,

			<&gcc GPLL0_AO_OUT_MAIN>;

		clock-names = "xo_ao", "gpll0_ao" ;

		reg =   <0xb011050 0x8>,

			<0xb1d1050 0x8>,

			<0xb016000 0x34>,

			<0x00a412c 0x8>;

		reg-names = "apcs-c1-rcg-base",

			"apcs-cci-rcg-base", "apcs_pll", "efuse";

		cpu-vdd-supply = <&apc_vreg_corner>;

		vdd_dig_ao-supply = <&L12A_AO;

		vdd_hf_pll-supply = <&VDD_CX_LEVEL_AO>;

		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1958400000 5>;



		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed1-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1804800000 5>;



		qcom,speed1-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed4-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1958400000 5>,

			< 2016000000 6>;



		qcom,speed4-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed5-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>;



		qcom,speed5-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		#clock-cells = <1>;

	};

arch/arm/configs/vendor/sdm429-bg-perf_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -508,6 +508,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y 
CONFIG_SPMI_PMIC_CLKDIV=y

CONFIG_SDM_GCC_429W=y

CONFIG_SDM_DEBUGCC_429W=y

CONFIG_CLOCK_CPU_SDM=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_MAILBOX=y

arch/arm/configs/vendor/sdm429-bg_defconfig

+1 −0
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@@ -523,6 +523,7 @@ CONFIG_QCOM_MDSS_PLL=y 
CONFIG_QCOM_CLK_SMD_RPM=y

CONFIG_SDM_GCC_429W=y

CONFIG_SDM_DEBUGCC_429W=y

CONFIG_CLOCK_CPU_SDM=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_MAILBOX=y

arch/arm64/boot/dts/qcom/sdm429.dtsi

+72 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/clock/mdss-12nm-pll-clk.h>

#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>

#include <dt-bindings/clock/qcom,cpu-sdm.h>



/ {

	model = "Qualcomm Technologies, Inc. SDM429";
@@ -341,6 +342,77 @@ 
		#clock-cells = <1>;

	};



	cpu: qcom,clock-cpu@b011050 {

		compatible = "qcom,cpu-clock-sdm";

		reg =   <0xb011050 0x8>,

			<0xb1d1050 0x8>,

			<0xB016000 0x34>,

			<0x00a412c 0x8>,

			<0x0b011200 0x100>;

		reg-names = "apcs-c1-rcg-base",

			"apcs-cci-rcg-base", "apcs_pll", "efuse",

			"spm_c1_base";

		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,

			<&gcc GPLL0_AO_OUT_MAIN>;

		clock-names = "xo_ao", "gpll0_ao" ;

		cpu-vdd-supply = <&apc_vreg_corner>;

		vdd_hf_pll-supply = <&L12A_AO>;

		vdd_dig_ao-supply = <&VDD_CX_LEVEL_AO>;

		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1958400000 5>;



		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed1-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1804800000 5>;



		qcom,speed1-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed4-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1958400000 5>,

			< 2016000000 6>;



		qcom,speed4-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed5-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>;



		qcom,speed5-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		#clock-cells = <1>;

	};



	cpu-pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <1 7 0xff00>;

drivers/clk/qcom/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -688,3 +688,11 @@ config SDM_DEBUGCC_429W 
	  Support for the debug clock controller on Qualcomm Technologies, Inc

	  SDM429W devices.

	  Say Y if you want to support the clock measurement functionality.



config CLOCK_CPU_SDM

	bool "CPU SDM Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	 Support for the cpu clock controller on SDM based devices(e.g. SDM429).

	 Say Y if you want to support CPU clock scaling using

	 CPUfreq drivers for dynamic power management.