Merge "drm/msm/sde: update mode-2 entry/exit sequence" into dev/msm-4.14-display (3049a6d2) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/gpu/drm/msm/sde_rsc_hw.c

+23 −4

Original line number	Diff line number	Diff line
		@@ -488,6 +488,9 @@ static int sde_rsc_mode2_exit(struct sde_rsc_priv *rsc,
		if (rc)
		pr_err("vdd reg is not enabled yet\n");

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0,
		0x3, rsc->debug_mode);

		rsc_event_trigger(rsc, SDE_RSC_EVENT_POST_CORE_RESTORE);

		return rc;
		@@ -560,19 +563,33 @@ static void sde_rsc_reset_mode_0_1(struct sde_rsc_priv *rsc)

		if (seq_busy && (current_mode == SDE_RSC_MODE_0_VAL \|\|
		current_mode == SDE_RSC_MODE_1_VAL)) {
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,
		0xffffffff, rsc->debug_mode);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_HI,
		0xffffff, rsc->debug_mode);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,
		0xffffffff, rsc->debug_mode);
		/* unstick f1 qtimer */
		wmb();

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,
		0x0, rsc->debug_mode);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_HI,
		0x0, rsc->debug_mode);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,
		0x0, rsc->debug_mode);
		/* manually trigger f1 qtimer interrupt */
		wmb();

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_HI,
		0xffffff, rsc->debug_mode);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_LO,
		0xffffffff, rsc->debug_mode);
		/* unstick f0 qtimer */
		wmb();

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_HI,
		0x0, rsc->debug_mode);
		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_LO,
		0x0, rsc->debug_mode);
		/* manually trigger f0 qtimer interrupt */
		wmb();
		}
		}

		@@ -590,6 +607,8 @@ static int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc)
		return rc;
		}

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0,
		0x7, rsc->debug_mode);
		rsc_event_trigger(rsc, SDE_RSC_EVENT_PRE_CORE_PC);

		for (i = 0; i <= MAX_MODE2_ENTRY_TRY; i++) {