Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 53d88e8d authored by Dhaval Patel's avatar Dhaval Patel
Browse files

drm/msm/sde: update mode-2 entry/exit sequence 



Disable mode-2 selection from RSC hardware after
sw has triggered it manually. This avoids double
shutdown issue if panel does not generate a vsync
after solver enabled. The change also updates F0
Qtimer trigger for mode_2 entry triggered during
mode_0 or mode_1.

Change-Id: Ic7a993acbdb7cdeb4ff9654846b430cdf0938d7a
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent e86dee8e

drivers/gpu/drm/msm/sde_rsc_hw.c

+23 −4
Original line number Diff line number Diff line
@@ -488,6 +488,9 @@ static int sde_rsc_mode2_exit(struct sde_rsc_priv *rsc, 
	if (rc)

		pr_err("vdd reg is not enabled yet\n");



	dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0,

						0x3, rsc->debug_mode);



	rsc_event_trigger(rsc, SDE_RSC_EVENT_POST_CORE_RESTORE);



	return rc;
@@ -560,19 +563,33 @@ static void sde_rsc_reset_mode_0_1(struct sde_rsc_priv *rsc) 


	if (seq_busy && (current_mode == SDE_RSC_MODE_0_VAL ||

			current_mode == SDE_RSC_MODE_1_VAL)) {

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,

						0xffffffff, rsc->debug_mode);

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_HI,

						0xffffff, rsc->debug_mode);

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,

						0xffffffff, rsc->debug_mode);

		/* unstick f1 qtimer */

		wmb();



		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,

						0x0, rsc->debug_mode);

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_HI,

						0x0, rsc->debug_mode);

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,

						0x0, rsc->debug_mode);

		/* manually trigger f1 qtimer interrupt */

		wmb();



		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_HI,

						0xffffff, rsc->debug_mode);

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_LO,

						0xffffffff, rsc->debug_mode);

		/* unstick f0 qtimer */

		wmb();



		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_HI,

						0x0, rsc->debug_mode);

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_LO,

						0x0, rsc->debug_mode);

		/* manually trigger f0 qtimer interrupt */

		wmb();

	}

}
@@ -590,6 +607,8 @@ static int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc) 
		return rc;

	}



	dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0,

						0x7, rsc->debug_mode);

	rsc_event_trigger(rsc, SDE_RSC_EVENT_PRE_CORE_PC);



	for (i = 0; i <= MAX_MODE2_ENTRY_TRY; i++) {