Merge "clk: qcom: gcc: Add support for additional clock for QCS405" (27d19b53) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/clk/qcom/clk-smd-rpm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -606,7 +606,7 @@ DEFINE_CLK_SMD_RPM_QDSS(qcs405, qdss_clk, qdss_a_clk,
		DEFINE_CLK_SMD_RPM(qcs405, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
		DEFINE_CLK_SMD_RPM(qcs405, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
		DEFINE_CLK_SMD_RPM(qcs405, bimc_gpu_clk, bimc_gpu_a_clk,
		QCOM_SMD_RPM_MEM_CLK, 0);
		QCOM_SMD_RPM_MEM_CLK, 2);
		/* SMD_XO_BUFFER */
		DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, ln_bb_clk, ln_bb_clk_a, 8);
		DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, rf_clk1, rf_clk1_a, 4);

drivers/clk/qcom/gcc-qcs405.c

+32 −4

Original line number	Diff line number	Diff line
		@@ -443,7 +443,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
		.freq_tbl = ftbl_apss_ahb_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "apss_ahb_clk_src",
		.parent_names = gcc_parent_names_0,
		.parent_names = gcc_parent_names_ao_0,
		.num_parents = 3,
		.ops = &clk_rcg2_ops,
		},
		@@ -1480,6 +1480,19 @@ static struct clk_branch gcc_dcc_clk = {
		},
		};

		static struct clk_branch gcc_dcc_xo_clk = {
		.halt_reg = 0x77008,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x77008,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_dcc_xo_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {
		.halt_reg = 0x6028,
		.halt_check = BRANCH_HALT,
		@@ -1926,6 +1939,19 @@ static struct clk_branch gcc_geni_ir_s_clk = {
		},
		};

		static struct clk_branch gcc_geni_ir_h_clk = {
		.halt_reg = 0xf004,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0xf004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_geni_ir_h_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_gfx_tcu_clk = {
		.halt_reg = 0x12020,
		.halt_check = BRANCH_VOTED,
		@@ -2698,7 +2724,7 @@ static struct clk_branch gcc_usb_hs_system_clk = {
		static struct clk_dummy wcnss_m_clk = {
		.rrate = 1000,
		.hw.init = &(struct clk_init_data){
		.name = "wcss_m_clk",
		.name = "wcnss_m_clk",
		.ops = &clk_dummy_ops,
		},
		};
		@@ -2753,6 +2779,7 @@ static struct clk_regmap *gcc_qcs405_clocks[] = {
		[GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
		[GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
		[GCC_GENI_IR_S_CLK] = &gcc_geni_ir_s_clk.clkr,
		[GCC_GENI_IR_H_CLK] = &gcc_geni_ir_h_clk.clkr,
		[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
		[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
		[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
		@@ -2834,6 +2861,7 @@ static struct clk_regmap *gcc_qcs405_clocks[] = {
		[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
		[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
		[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
		[GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
		};

		static const struct qcom_reset_map gcc_qcs405_resets[] = {
		@@ -2841,8 +2869,8 @@ static const struct qcom_reset_map gcc_qcs405_resets[] = {
		[GCC_USB_HS_BCR] = {0x41000},
		[GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034},
		[GCC_QUSB2_PHY_BCR] = {0x4103C},
		[GCC_USB_HS_PHY_CFG_AHB_BCR] = {0x0000C, 0},
		[GCC_USB2A_PHY_BCR] = {0x0000C, 1},
		[GCC_USB_HS_PHY_CFG_AHB_BCR] = {0x0000C, 1},
		[GCC_USB2A_PHY_BCR] = {0x0000C, 0},
		[GCC_USB3_PHY_BCR] = {0x39004},
		[GCC_USB_30_BCR] = {0x39000},
		[GCC_USB3PHY_PHY_BCR] = {0x39008},

include/dt-bindings/clock/qcom,gcc-qcs405.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -154,6 +154,7 @@
		#define GCC_CRYPTO_CLK 137
		#define GCC_MDP_TBU_CLK 138
		#define GCC_QDSS_DAP_CLK 139
		#define GCC_DCC_XO_CLK 140

		#define GCC_GENI_IR_BCR 0
		#define GCC_USB_HS_BCR 1