Merge "clk: qcom: mdss: fix reg_read/reg_write callbacks for DSI 28nm PLL" (2983380c) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/clk/qcom/mdss/mdss-dsi-pll-28lpm.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -210,7 +210,7 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
		.lpfr_lut = lpfr_lut_struct,
		.hw.init = &(struct clk_init_data){
		.name = "dsi0pll_vco_clk",
		.parent_names = (const char *[]){"bi_tcxo"},
		.parent_names = (const char *[]){"cxo"},
		.num_parents = 1,
		.ops = &clk_ops_vco_28lpm,
		.flags = CLK_GET_RATE_NOCACHE,
		@@ -235,7 +235,7 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
		.lpfr_lut = lpfr_lut_struct,
		.hw.init = &(struct clk_init_data){
		.name = "dsi1pll_vco_clk",
		.parent_names = (const char *[]){"bi_tcxo"},
		.parent_names = (const char *[]){"cxo"},
		.num_parents = 1,
		.ops = &clk_ops_vco_28lpm,
		.flags = CLK_GET_RATE_NOCACHE,

drivers/clk/qcom/mdss/mdss-dsi-pll-28nm-util.c

+8 −42

Original line number	Diff line number	Diff line
		@@ -61,9 +61,6 @@ int analog_postdiv_reg_read(void *context, unsigned int reg,
		int rc = 0;
		struct mdss_pll_resources *rsc = context;

		if (is_gdsc_disabled(rsc))
		return 0;

		rc = mdss_pll_resource_enable(rsc, true);
		if (rc) {
		pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
		@@ -72,13 +69,6 @@ int analog_postdiv_reg_read(void *context, unsigned int reg,

		*div = MDSS_PLL_REG_R(rsc->pll_base, reg);

		/**
		* Common clock framework the divider value is interpreted as one less
		* hence we return one less for all dividers except when zero
		*/
		if (*div != 0)
		*div -= 1;

		pr_debug("analog_postdiv div = %d\n", *div);

		(void)mdss_pll_resource_enable(rsc, false);
		@@ -99,13 +89,6 @@ int analog_postdiv_reg_write(void *context, unsigned int reg,

		pr_debug("analog_postdiv div = %d\n", div);

		/**
		* In common clock framework the divider value provided is one less and
		* and hence adjusting the divider value by one prior to writing it to
		* hardware
		*/
		div++;

		MDSS_PLL_REG_W(rsc->pll_base, reg, div);

		(void)mdss_pll_resource_enable(rsc, false);
		@@ -118,16 +101,13 @@ int byteclk_mux_read_sel(void *context, unsigned int reg,
		int rc = 0;
		struct mdss_pll_resources *rsc = context;

		if (is_gdsc_disabled(rsc))
		return 0;

		rc = mdss_pll_resource_enable(rsc, true);
		if (rc) {
		pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
		return rc;
		}

		*val = ((MDSS_PLL_REG_R(rsc->pll_base, reg) & BIT(1)) >> 1);
		*val = (MDSS_PLL_REG_R(rsc->pll_base, reg) & BIT(1));
		pr_debug("byteclk mux mode = %s", *val ? "indirect" : "direct");

		(void)mdss_pll_resource_enable(rsc, false);
		@@ -151,7 +131,7 @@ int byteclk_mux_write_sel(void *context, unsigned int reg,

		reg_val = MDSS_PLL_REG_R(rsc->pll_base, reg);
		reg_val &= ~0x02;
		reg_val \|= (val << 1);
		reg_val \|= val;

		MDSS_PLL_REG_W(rsc->pll_base, reg, reg_val);

		@@ -166,9 +146,6 @@ int pixel_clk_get_div(void *context, unsigned int reg,
		int rc = 0;
		struct mdss_pll_resources *rsc = context;

		if (is_gdsc_disabled(rsc))
		return 0;

		rc = mdss_pll_resource_enable(rsc, true);
		if (rc) {
		pr_err("Failed to enable dsi pll resources, rc=%d\n", rc);
		@@ -177,13 +154,6 @@ int pixel_clk_get_div(void *context, unsigned int reg,

		*div = MDSS_PLL_REG_R(rsc->pll_base, reg);

		/**
		*Common clock framework the divider value is interpreted as one less
		* hence we return one less for all dividers except when zero
		*/
		if (*div != 0)
		*div -= 1;

		pr_debug("pclk_src div = %d\n", *div);

		(void)mdss_pll_resource_enable(rsc, false);
		@@ -204,13 +174,6 @@ int pixel_clk_set_div(void *context, unsigned int reg,

		pr_debug("pclk_src div = %d\n", div);

		/**
		* In common clock framework the divider value provided is one less and
		* and hence adjusting the divider value by one prior to writing it to
		* hardware
		*/
		div++;

		MDSS_PLL_REG_W(rsc->pll_base, reg, div);

		(void)mdss_pll_resource_enable(rsc, false);
		@@ -414,6 +377,8 @@ static void pll_28nm_vco_config(struct dsi_pll_vco_clk *vco,
		MDSS_PLL_REG_W(pll_base, DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG11,
		(u32)(vco_calc->cal_cfg11 & 0xff));
		MDSS_PLL_REG_W(pll_base, DSI_PHY_PLL_UNIPHY_PLL_EFUSE_CFG, 0x20);
		MDSS_PLL_REG_W(pll_base,
		DSI_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG, 0x3); /* Fixed div-4 */
		}

		static int vco_set_rate(struct dsi_pll_vco_clk *vco, unsigned long rate)
		@@ -442,9 +407,6 @@ static unsigned long vco_get_rate(struct dsi_pll_vco_clk *vco)
		u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
		u64 ref_clk = vco->ref_clk_rate;

		if (is_gdsc_disabled(rsc))
		return 0;

		rc = mdss_pll_resource_enable(rsc, true);
		if (rc) {
		pr_err("Failed to enable mdss dsi pll resources\n");
		@@ -576,6 +538,7 @@ int vco_28nm_set_rate(struct clk_hw *hw, unsigned long rate,
		udelay(1000);

		rc = vco_set_rate(vco, rate);
		rsc->vco_current_rate = rate;

		mdss_pll_resource_enable(rsc, false);

		@@ -611,6 +574,9 @@ unsigned long vco_28nm_recalc_rate(struct clk_hw *hw,
		return 0;
		}

		if (rsc->vco_current_rate)
		return (unsigned long)rsc->vco_current_rate;

		if (is_gdsc_disabled(rsc))
		return 0;