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Commit 22842d24 authored by Chander Kashyap's avatar Chander Kashyap Committed by Tomasz Figa
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clk: samsung: exynos5260: fix typo in clock name



The parent name added in parent list as
mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, is different
than the defined parent due to typo.

Signed-off-by: default avatarAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: default avatarChander Kashyap <k.chander@samsung.com>
Signed-off-by: default avatarPankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: default avatarTomasz Figa <tomasz.figa@gmail.com>
parent e82ba578
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+1 −1
Original line number Original line Diff line number Diff line
@@ -1581,7 +1581,7 @@ struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
	FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
	FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
			NULL, CLK_IS_ROOT, 125000000),
			NULL, CLK_IS_ROOT, 125000000),
	FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
	FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
			"phyclk_mipi_dphy_4l_m_txbyteclkhs" , NULL,
			"phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
			CLK_IS_ROOT, 187500000),
			CLK_IS_ROOT, 187500000),
	FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
	FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
			NULL, CLK_IS_ROOT, 24000000),
			NULL, CLK_IS_ROOT, 24000000),