Merge "msm: kgsl: Enable APRIV control for targets that support it" (2073215c) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/gpu/msm/adreno-gpulist.h

+4 −3

Original line number	Diff line number	Diff line
		@@ -1028,7 +1028,8 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = {
		DEFINE_ADRENO_REV(ADRENO_REV_A620, 6, 2, 0, ANY_ID),
		.features = ADRENO_64BIT \| ADRENO_RPMH \| ADRENO_GPMU \|
		ADRENO_CONTENT_PROTECTION \| ADRENO_IOCOHERENT \|
		ADRENO_IFPC \| ADRENO_PREEMPTION \| ADRENO_ACD,
		ADRENO_IFPC \| ADRENO_PREEMPTION \| ADRENO_ACD \|
		ADRENO_APRIV,
		.gpudev = &adreno_a6xx_gpudev,
		.gmem_base = 0,
		.gmem_size = SZ_512K,
		@@ -1198,7 +1199,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = {
		DEFINE_ADRENO_REV(ADRENO_REV_A650, 6, 5, 0, 0),
		.features = ADRENO_64BIT \| ADRENO_RPMH \| ADRENO_GPMU \|
		ADRENO_IOCOHERENT \| ADRENO_CONTENT_PROTECTION \|
		ADRENO_IFPC,
		ADRENO_IFPC \| ADRENO_APRIV,
		.gpudev = &adreno_a6xx_gpudev,
		.gmem_base = 0,
		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
		@@ -1227,7 +1228,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = {
		.features = ADRENO_64BIT \| ADRENO_RPMH \| ADRENO_GPMU \|
		ADRENO_IOCOHERENT \| ADRENO_CONTENT_PROTECTION \|
		ADRENO_IFPC \| ADRENO_PREEMPTION \| ADRENO_ACD \|
		ADRENO_LM,
		ADRENO_LM \| ADRENO_APRIV,
		.gpudev = &adreno_a6xx_gpudev,
		.gmem_base = 0,
		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

drivers/gpu/msm/adreno.c

+16 −3

Original line number	Diff line number	Diff line
		@@ -1343,6 +1343,7 @@ static int adreno_probe(struct platform_device *pdev)
		struct adreno_device *adreno_dev;
		struct kgsl_device *device;
		int status;
		unsigned int priv;

		of_id = of_match_device(adreno_match_table, &pdev->dev);
		if (!of_id)
		@@ -1428,8 +1429,14 @@ static int adreno_probe(struct platform_device *pdev)
		device->mmu.features \|= KGSL_MMU_IO_COHERENT;

		/* Allocate the memstore for storing timestamps and other useful info */
		priv = KGSL_MEMDESC_CONTIG;

		if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))
		priv \|= KGSL_MEMDESC_PRIVILEGED;

		status = kgsl_allocate_global(device, &device->memstore,
		KGSL_MEMSTORE_SIZE, 0, KGSL_MEMDESC_CONTIG, "memstore");
		KGSL_MEMSTORE_SIZE, 0, priv, "memstore");

		if (status)
		goto out;

		@@ -1739,9 +1746,15 @@ static int adreno_init(struct kgsl_device *device)
		*/

		if (!adreno_is_a3xx(adreno_dev)) {
		int r = kgsl_allocate_global(device,
		unsigned int priv = 0;
		int r;

		if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))
		priv \|= KGSL_MEMDESC_PRIVILEGED;

		r = kgsl_allocate_global(device,
		&adreno_dev->profile_buffer, PAGE_SIZE,
		0, 0, "alwayson");
		0, priv, "alwayson");

		adreno_dev->profile_index = 0;

drivers/gpu/msm/adreno.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -107,6 +107,8 @@
		#define ADRENO_COOP_RESET BIT(19)
		/* Indicates that the specific target is no longer supported */
		#define ADRENO_DEPRECATED BIT(20)
		/* The target supports ringbuffer level APRIV */
		#define ADRENO_APRIV BIT(21)
		/*
		* Adreno GPU quirks - control bits for various workarounds
		*/

drivers/gpu/msm/adreno_a6xx.c

+22 −12

Original line number	Diff line number	Diff line
		@@ -743,7 +743,8 @@ static int _preemption_init(struct adreno_device *adreno_dev,
		{
		unsigned int *cmds_orig = cmds;

		/* Turn CP protection OFF */
		/* Turn CP protection OFF on legacy targets */
		if (!ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))
		cmds += cp_protected_mode(adreno_dev, cmds, 0);

		*cmds++ = cp_type7_packet(CP_SET_PSEUDO_REGISTER, 6);
		@@ -755,7 +756,8 @@ static int _preemption_init(struct adreno_device *adreno_dev,
		cmds += cp_gpuaddr(adreno_dev, cmds,
		rb->secure_preemption_desc.gpuaddr);

		/* Turn CP protection ON */
		/* Turn CP protection back ON */
		if (!ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))
		cmds += cp_protected_mode(adreno_dev, cmds, 1);

		*cmds++ = cp_type7_packet(CP_CONTEXT_SWITCH_YIELD, 4);
		@@ -797,6 +799,20 @@ static int a6xx_post_start(struct adreno_device *adreno_dev)
		return ret;
		}

		/*
		* Some targets support marking certain transactions as always privileged which
		* allows us to mark more memory as privileged without having to explicitly set
		* the APRIV bit. For those targets, choose the following transactions to be
		* privileged by default:
		* CDWRITE [6:6] - Crashdumper writes
		* CDREAD [5:5] - Crashdumper reads
		* RBRPWB [3:3] - RPTR shadow writes
		* RBPRIVLEVEL [2:2] - Memory accesses from PM4 packets in the ringbuffer
		* RBFETCH [1:1] - Ringbuffer reads
		*/
		#define A6XX_APRIV_DEFAULT \
		((1 << 6) \| (1 << 5) \| (1 << 3) \| (1 << 2) \| (1 << 1))

		/*
		* a6xx_rb_start() - Start the ringbuffer
		* @adreno_dev: Pointer to adreno device
		@@ -827,14 +843,8 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev)
		if (ret)
		return ret;

		/*
		* Set the RBPRIVLEVEL bit in this register to determine
		* the privilege level of ucode executing packets in the RB,
		* so we can come out of secure mode and CP does not drop
		* the packet.
		*/
		if (adreno_is_a650_family(adreno_dev))
		kgsl_regwrite(device, A6XX_CP_APRIV_CNTL, (1 << 2));
		if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))
		kgsl_regwrite(device, A6XX_CP_APRIV_CNTL, A6XX_APRIV_DEFAULT);

		/* Clear the SQE_HALT to start the CP engine */
		kgsl_regwrite(device, A6XX_CP_SQE_CNTL, 1);

drivers/gpu/msm/adreno_a6xx_snapshot.c

+5 −3

Original line number	Diff line number	Diff line
		@@ -1606,7 +1606,8 @@ static void _a6xx_do_crashdump(struct kgsl_device *device)
		if (val & BIT(24))
		return;

		/* Turn on APRIV so we can access the buffers */
		/* Turn on APRIV for legacy targets so we can access the buffers */
		if (!ADRENO_FEATURE(ADRENO_DEVICE(device), ADRENO_APRIV))
		kgsl_regwrite(device, A6XX_CP_MISC_CNTL, 1);

		kgsl_regwrite(device, A6XX_CP_CRASH_SCRIPT_BASE_LO,
		@@ -1623,6 +1624,7 @@ static void _a6xx_do_crashdump(struct kgsl_device *device)
		cpu_relax();
		}

		if (!ADRENO_FEATURE(ADRENO_DEVICE(device), ADRENO_APRIV))
		kgsl_regwrite(device, A6XX_CP_MISC_CNTL, 0);

		if (!(reg & 0x2)) {