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Commit 1ff487f3 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: qcom: limit sdhci clk rate to 100MHz for sdio"

parents d87f4978 950ecffb

arch/arm64/boot/dts/qcom/mdm9607.dtsi

+1 −2
Original line number Diff line number Diff line
@@ -845,8 +845,7 @@ 
		      <&tlmm_pinmux 12 0>; /* DATA3 */

		qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";



		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000

			200000000>;

		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>;



		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,