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Commit 1def75fd authored by Odelu Kukatla's avatar Odelu Kukatla Committed by Gerrit - the friendly Code Review server
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clk: qcom: Enable Clock Ramp Controller(CRC) for GFX3D clock for SM6150 



Clock Ramp Controller(CRC) is an HW modlue inside gfx3d clock's
Root Clock Generator(RCG), capable of ramp down/up operation to
mitigate the PDN droop by reducing the clock frequency during
dynamic clock switch operation. And CRC module interfaces with
LMH hardware to throttle the clock during thermal/max current
mitigation operation.

Change-Id: Iac78c262221bff57b9c46207634703c131617cb9
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
parent ec453551

drivers/clk/qcom/gpucc-sm6150.c

+54 −13
Original line number Diff line number Diff line
@@ -37,6 +37,8 @@ 
#define CX_GMU_CBCR_SLEEP_SHIFT		4

#define CX_GMU_CBCR_WAKE_MASK		0xf

#define CX_GMU_CBCR_WAKE_SHIFT		8

#define GFX3D_CRC_SID_FSM_CTRL		0x1024

#define GFX3D_CRC_MND_CFG		0x1028



#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -49,10 +51,10 @@ enum { 
	P_GPLL0_OUT_MAIN,

	P_GPLL0_OUT_MAIN_DIV,

	P_GPU_CC_PLL0_2X_CLK,

	P_GPU_CC_PLL0_OUT_AUX2,

	P_CRC_DIV_PLL0_OUT_AUX2,

	P_GPU_CC_PLL0_OUT_MAIN,

	P_GPU_CC_PLL1_OUT_AUX,

	P_GPU_CC_PLL1_OUT_AUX2,

	P_CRC_DIV_PLL1_OUT_AUX2,

	P_GPU_CC_PLL1_OUT_MAIN,

};
@@ -77,9 +79,9 @@ static const char * const gpu_cc_parent_names_0[] = { 
static const struct parent_map gpu_cc_parent_map_1[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPU_CC_PLL0_2X_CLK, 1 },

	{ P_GPU_CC_PLL0_OUT_AUX2, 2 },

	{ P_CRC_DIV_PLL0_OUT_AUX2, 2 },

	{ P_GPU_CC_PLL1_OUT_AUX, 3 },

	{ P_GPU_CC_PLL1_OUT_AUX2, 4 },

	{ P_CRC_DIV_PLL1_OUT_AUX2, 4 },

	{ P_GPLL0_OUT_MAIN, 5 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};
@@ -87,9 +89,9 @@ static const struct parent_map gpu_cc_parent_map_1[] = { 
static const char * const gpu_cc_parent_names_1[] = {

	"bi_tcxo",

	"gpu_cc_pll0_out_aux",

	"gpu_cc_pll0_out_aux2",

	"crc_div_pll0_out_aux2",

	"gpu_cc_pll1_out_aux",

	"gpu_cc_pll1_out_aux2",

	"crc_div_pll1_out_aux2",

	"gpll0_out_main",

	"core_bi_pll_test_se",

};
@@ -189,14 +191,38 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { 
	},

};



static struct clk_fixed_factor crc_div_pll0_out_aux2 = {

	.mult = 1,

	.div = 2,

	.hw.init = &(struct clk_init_data){

		.name = "crc_div_pll0_out_aux2",

		.parent_names = (const char *[]){ "gpu_cc_pll0_out_aux2" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_fixed_factor_ops,

	},

};



static struct clk_fixed_factor crc_div_pll1_out_aux2 = {

	.mult = 1,

	.div = 2,

	.hw.init = &(struct clk_init_data){

		.name = "crc_div_pll1_out_aux2",

		.parent_names = (const char *[]){ "gpu_cc_pll1_out_aux2" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_fixed_factor_ops,

	},

};



static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {

	F(290000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),

	F(435000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),

	F(550000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),

	F(700000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),

	F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),

	F(845000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),

	F(895000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),

	F(290000000, P_CRC_DIV_PLL1_OUT_AUX2, 1, 0, 0),

	F(435000000, P_CRC_DIV_PLL1_OUT_AUX2, 1, 0, 0),

	F(550000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),

	F(700000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),

	F(745000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),

	F(845000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),

	F(895000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0),

	{ }

};
@@ -408,6 +434,11 @@ static struct clk_branch gpu_cc_ahb_clk = { 
	},

};



struct clk_hw *gpu_cc_sm6150_hws[] = {

	[CRC_DIV_PLL0_OUT_AUX2] = &crc_div_pll0_out_aux2.hw,

	[CRC_DIV_PLL1_OUT_AUX2] = &crc_div_pll1_out_aux2.hw,

};



static struct clk_regmap *gpu_cc_sm6150_clocks[] = {

	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,

	[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
@@ -439,6 +470,8 @@ static const struct qcom_cc_desc gpu_cc_sm6150_desc = { 
	.config = &gpu_cc_sm6150_regmap_config,

	.clks = gpu_cc_sm6150_clocks,

	.num_clks = ARRAY_SIZE(gpu_cc_sm6150_clocks),

	.hwclks = gpu_cc_sm6150_hws,

	.num_hwclks = ARRAY_SIZE(gpu_cc_sm6150_hws),

};



static const struct of_device_id gpu_cc_sm6150_match_table[] = {
@@ -495,6 +528,14 @@ static int gpu_cc_sm6150_probe(struct platform_device *pdev) 
	regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,

							mask, value);



	/* After POR, Clock Ramp Controller(CRC) will be in bypass mode.

	 * Software needs to do the following operation to enable the CRC

	 * for GFX3D clock and divide the input clock by div by 2.

	 */

	regmap_update_bits(regmap, GFX3D_CRC_MND_CFG, 0x00015011, 0x00015011);

	regmap_update_bits(regmap,

			GFX3D_CRC_SID_FSM_CTRL, 0x00800000, 0x00800000);



	dev_info(&pdev->dev, "Registered GPU CC clocks\n");



	return ret;

include/dt-bindings/clock/qcom,gpucc-sm6150.h

+21 −17
Original line number Diff line number Diff line
@@ -14,23 +14,27 @@ 
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6150_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6150_H



/* Hardware clocks */

#define CRC_DIV_PLL0_OUT_AUX2			0

#define CRC_DIV_PLL1_OUT_AUX2			1



/* GPUCC clock registers */

#define GPU_CC_PLL0_OUT_AUX2			0

#define GPU_CC_PLL1_OUT_AUX2			1

#define GPU_CC_CRC_AHB_CLK			2

#define GPU_CC_CX_APB_CLK			3

#define GPU_CC_CX_GFX3D_CLK			4

#define GPU_CC_CX_GFX3D_SLV_CLK			5

#define GPU_CC_CX_GMU_CLK			6

#define GPU_CC_CX_SNOC_DVM_CLK			7

#define GPU_CC_CXO_AON_CLK			8

#define GPU_CC_CXO_CLK				9

#define GPU_CC_GMU_CLK_SRC			10

#define GPU_CC_SLEEP_CLK			11

#define GPU_CC_GX_GMU_CLK			12

#define GPU_CC_GX_CXO_CLK			13

#define GPU_CC_GX_GFX3D_CLK			14

#define GPU_CC_GX_GFX3D_CLK_SRC			15

#define GPU_CC_AHB_CLK				16

#define GPU_CC_PLL0_OUT_AUX2			2

#define GPU_CC_PLL1_OUT_AUX2			3

#define GPU_CC_CRC_AHB_CLK			4

#define GPU_CC_CX_APB_CLK			5

#define GPU_CC_CX_GFX3D_CLK			6

#define GPU_CC_CX_GFX3D_SLV_CLK			7

#define GPU_CC_CX_GMU_CLK			8

#define GPU_CC_CX_SNOC_DVM_CLK			9

#define GPU_CC_CXO_AON_CLK			10

#define GPU_CC_CXO_CLK				11

#define GPU_CC_GMU_CLK_SRC			12

#define GPU_CC_SLEEP_CLK			13

#define GPU_CC_GX_GMU_CLK			14

#define GPU_CC_GX_CXO_CLK			15

#define GPU_CC_GX_GFX3D_CLK			16

#define GPU_CC_GX_GFX3D_CLK_SRC			17

#define GPU_CC_AHB_CLK				18



#endif