clk: qcom: gcc-qcs405: Add support for vdd_sr_pll regulator

SR PLL is connected to LDO3 so GPLL6 should vote for this
rail when there is a frequency request. Add support for
voting for this rail.

Change-Id: I264daffb2de2b6461e2fdbced96454a21ec29a12
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>