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Commit 18cae6f7 authored by Todd Fujinaka's avatar Todd Fujinaka Committed by Jeff Kirsher
Browse files

igb: remove redundant PHY power down register write 



One of the registers used to power down the PHY was found to be wrong
(should be bit 2 not bit 1) on further inspection it was also found to
be redundant.

Signed-off-by: default avatarTodd Fujinaka <todd.fujinaka@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent c6f3148c

drivers/net/ethernet/intel/igb/e1000_phy.c

+0 −14
Original line number Diff line number Diff line
@@ -2204,16 +2204,10 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw) 
void igb_power_up_phy_copper(struct e1000_hw *hw)

{

	u16 mii_reg = 0;

	u16 power_reg = 0;



	/* The PHY will retain its settings across a power down/up cycle */

	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);

	mii_reg &= ~MII_CR_POWER_DOWN;

	if (hw->phy.type == e1000_phy_i210) {

		hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);

		power_reg &= ~GS40G_CS_POWER_DOWN;

		hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);

	}

	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

}
@@ -2227,18 +2221,10 @@ void igb_power_up_phy_copper(struct e1000_hw *hw) 
void igb_power_down_phy_copper(struct e1000_hw *hw)

{

	u16 mii_reg = 0;

	u16 power_reg = 0;



	/* The PHY will retain its settings across a power down/up cycle */

	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);

	mii_reg |= MII_CR_POWER_DOWN;



	/* i210 Phy requires an additional bit for power up/down */

	if (hw->phy.type == e1000_phy_i210) {

		hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);

		power_reg |= GS40G_CS_POWER_DOWN;

		hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);

	}

	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);

	usleep_range(1000, 2000);

}

drivers/net/ethernet/intel/igb/e1000_phy.h

+0 −1
Original line number Diff line number Diff line
@@ -151,7 +151,6 @@ s32 igb_check_polarity_m88(struct e1000_hw *hw); 
#define GS40G_MAC_LB			0x4140

#define GS40G_MAC_SPEED_1G		0X0006

#define GS40G_COPPER_SPEC		0x0010

#define GS40G_CS_POWER_DOWN		0x0002

#define GS40G_LINE_LB			0x4000



/* SFP modules ID memory locations */