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Commit c6f3148c authored by Andi Kleen's avatar Andi Kleen Committed by Jeff Kirsher
Browse files

e1000e: Out of line __ew32_prepare/__ew32 



Out of lining these two common inlines saves about 30k text size,
due to their errata workarounds.

14131431	2008136	1507328	17646895	10d452f	vmlinux-before-e1000e
14101415	2004040	1507328	17612783	10cbfef	vmlinux-e1000e

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 50844bb7

drivers/net/ethernet/intel/e1000e/e1000.h

+2 −29
Original line number Diff line number Diff line
@@ -575,35 +575,8 @@ static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 


#define er32(reg)	__er32(hw, E1000_##reg)



/**

 * __ew32_prepare - prepare to write to MAC CSR register on certain parts

 * @hw: pointer to the HW structure

 *

 * When updating the MAC CSR registers, the Manageability Engine (ME) could

 * be accessing the registers at the same time.  Normally, this is handled in

 * h/w by an arbiter but on some parts there is a bug that acknowledges Host

 * accesses later than it should which could result in the register to have

 * an incorrect value.  Workaround this by checking the FWSM register which

 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set

 * and try again a number of times.

 **/

static inline s32 __ew32_prepare(struct e1000_hw *hw)

{

	s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;



	while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)

		udelay(50);



	return i;

}



static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)

{

	if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)

		__ew32_prepare(hw);



	writel(val, hw->hw_addr + reg);

}

s32 __ew32_prepare(struct e1000_hw *hw);

void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);



#define ew32(reg, val)	__ew32(hw, E1000_##reg, (val))

drivers/net/ethernet/intel/e1000e/netdev.c

+30 −0
Original line number Diff line number Diff line
@@ -123,6 +123,36 @@ static const struct e1000_reg_info e1000_reg_info_tbl[] = { 
	{0, NULL}

};



/**

 * __ew32_prepare - prepare to write to MAC CSR register on certain parts

 * @hw: pointer to the HW structure

 *

 * When updating the MAC CSR registers, the Manageability Engine (ME) could

 * be accessing the registers at the same time.  Normally, this is handled in

 * h/w by an arbiter but on some parts there is a bug that acknowledges Host

 * accesses later than it should which could result in the register to have

 * an incorrect value.  Workaround this by checking the FWSM register which

 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set

 * and try again a number of times.

 **/

s32 __ew32_prepare(struct e1000_hw *hw)

{

	s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;



	while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)

		udelay(50);



	return i;

}



void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)

{

	if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)

		__ew32_prepare(hw);



	writel(val, hw->hw_addr + reg);

}



/**

 * e1000_regdump - register printout routine

 * @hw: pointer to the HW structure