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Unverified Commit 11f65ad1 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

dt-bindings: riscv,cpu-intc: Cleanups from a missed review 

I managed to miss one of Rob's code reviews on the mailing list
<http://lists.infradead.org/pipermail/linux-riscv/2018-August/001139.html

>.
The patch has already been merged, so I'm submitting a fixup.

Sorry!

Fixes: b67bc7cb ("dt-bindings: interrupt-controller: RISC-V local interrupt controller")
Cc: Rob Herring <robh@kernel.org>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Karsten Merker <merker@debian.org>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 5b394b2d

Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt

+11 −3
Original line number Original line Diff line number Diff line
@@ -11,7 +11,7 @@ The RISC-V supervisor ISA manual specifies three interrupt sources that are 
attached to every HLIC: software interrupts, the timer interrupt, and external

attached to every HLIC: software interrupts, the timer interrupt, and external

interrupts.  Software interrupts are used to send IPIs between cores.  The

interrupts.  Software interrupts are used to send IPIs between cores.  The

timer interrupt comes from an architecturally mandated real-time timer that is

timer interrupt comes from an architecturally mandated real-time timer that is

controller via Supervisor Binary Interface (SBI) calls and CSR reads.  External

controlled via Supervisor Binary Interface (SBI) calls and CSR reads.  External

interrupts connect all other device interrupts to the HLIC, which are routed

interrupts connect all other device interrupts to the HLIC, which are routed

via the platform-level interrupt controller (PLIC).

via the platform-level interrupt controller (PLIC).
@@ -25,7 +25,15 @@ in the system. 




Required properties:

Required properties:

- compatible : "riscv,cpu-intc"

- compatible : "riscv,cpu-intc"

- #interrupt-cells : should be <1>

- #interrupt-cells : should be <1>.  The interrupt sources are defined by the

  RISC-V supervisor ISA manual, with only the following three interrupts being

  defined for supervisor mode:

    - Source 1 is the supervisor software interrupt, which can be sent by an SBI

      call and is reserved for use by software.

    - Source 5 is the supervisor timer interrupt, which can be configured by

      SBI calls and implements a one-shot timer.

    - Source 9 is the supervisor external interrupt, which chains to all other

      device interrupts.

- interrupt-controller : Identifies the node as an interrupt controller

- interrupt-controller : Identifies the node as an interrupt controller





Furthermore, this interrupt-controller MUST be embedded inside the cpu

Furthermore, this interrupt-controller MUST be embedded inside the cpu
@@ -38,7 +46,7 @@ An example device tree entry for a HLIC is show below. 
		...

		...

		cpu1-intc: interrupt-controller {

		cpu1-intc: interrupt-controller {

			#interrupt-cells = <1>;

			#interrupt-cells = <1>;

			compatible = "riscv,cpu-intc", "sifive,fu540-c000-cpu-intc";

			compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";

			interrupt-controller;

			interrupt-controller;

		};

		};

	};
 
	};