drm/msm/dsi-staging: fix clock gating sequence

Clock gating sequence needed to be fixed to ensure correct programming
of branch clock RCGs.  Clock gating is supposed to be turned on after 
PLL is prepared and while turning off the clock, clock gating 
needs to be disabled before the branch clocks are disabled.

Change-Id: Ib330e969f07ac97c14bf00b17040fbbf4327d350
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>