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Commit 0bc2e2b5 authored by Srinivas Ramana's avatar Srinivas Ramana Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add llcc cache dump support for sm6150



sm6150 supports a single instance Last level cache controller
with 256KB system cache. Add dump size to allocate buffers
for llcc cache dumps.

Change-Id: I86adc793df960667f623a5e8853e5b2b824b9ec3
Signed-off-by: default avatarSrinivas Ramana <sramana@codeaurora.org>
parent 0b3ec9bc
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