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Commit 0b0947ca authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ipa: fix to header proc context updatation"

parents 1c00cc03 a01f436e

drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c

+2 −1
Original line number Diff line number Diff line
@@ -100,7 +100,8 @@ static int ipa3_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem, 
				entry->hdr->phys_base,

				hdr_base_addr,

				entry->hdr->offset_entry,

				entry->l2tp_params);

				entry->l2tp_params,

				ipa3_ctx->use_64_bit_dma_mask);

		if (ret)

			return ret;

	}

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c

+38 −18
Original line number Diff line number Diff line
@@ -1189,6 +1189,13 @@ static void ipahal_cp_hdr_to_hw_buff_v3(void *const base, u32 offset, 
	memcpy(base + offset, hdr, hdr_len);

}



/* Header address update logic. */

#define IPAHAL_CP_PROC_CTX_HEADER_UPDATE(hdr_lsb, hdr_msb, addr) \

	do { \

		hdr_lsb = lower_32_bits(addr); \

		hdr_msb = upper_32_bits(addr); \

	} while (0)



/*

 * ipahal_cp_proc_ctx_to_hw_buff_v3() - copy processing context to

 * base address and offset given.
@@ -1202,26 +1209,31 @@ static void ipahal_cp_hdr_to_hw_buff_v3(void *const base, u32 offset, 
 * @hdr_base_addr: base address in table

 * @offset_entry: offset from hdr_base_addr in table

 * @l2tp_params: l2tp parameters

 * @is_64: Indicates whether header base address/dma base address is 64 bit.

 */

static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,

		void *const base, u32 offset,

		u32 hdr_len, bool is_hdr_proc_ctx,

		dma_addr_t phys_base, u64 hdr_base_addr,

		struct ipa_hdr_offset_entry *offset_entry,

		struct ipa_l2tp_hdr_proc_ctx_params l2tp_params)

		struct ipa_l2tp_hdr_proc_ctx_params l2tp_params, bool is_64)

{

	u64 hdr_addr;



	if (type == IPA_HDR_PROC_NONE) {

		struct ipa_hw_hdr_proc_ctx_add_hdr_seq *ctx;



		ctx = (struct ipa_hw_hdr_proc_ctx_add_hdr_seq *)

			(base + offset);

		ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;

		ctx->hdr_add.tlv.length = 1;

		ctx->hdr_add.tlv.length = is_64 ? 2 : 1;

		ctx->hdr_add.tlv.value = hdr_len;

		ctx->hdr_add.hdr_addr = is_hdr_proc_ctx ? phys_base :

		hdr_addr = is_hdr_proc_ctx ? phys_base :

			hdr_base_addr + offset_entry->offset;

		IPAHAL_DBG("header address 0x%llx\n",

			ctx->hdr_add.hdr_addr);

			hdr_addr);

		IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,

			ctx->hdr_add.hdr_addr_hi, hdr_addr);

		ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END;

		ctx->end.length = 0;

		ctx->end.value = 0;
@@ -1231,12 +1243,14 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type, 
		ctx = (struct ipa_hw_hdr_proc_ctx_add_l2tp_hdr_cmd_seq *)

			(base + offset);

		ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;

		ctx->hdr_add.tlv.length = 1;

		ctx->hdr_add.tlv.length = is_64 ? 2 : 1;

		ctx->hdr_add.tlv.value = hdr_len;

		ctx->hdr_add.hdr_addr = is_hdr_proc_ctx ? phys_base :

		hdr_addr = is_hdr_proc_ctx ? phys_base :

			hdr_base_addr + offset_entry->offset;

		IPAHAL_DBG("header address 0x%llx\n",

			ctx->hdr_add.hdr_addr);

			hdr_addr);

		IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,

			ctx->hdr_add.hdr_addr_hi, hdr_addr);

		ctx->l2tp_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD;

		ctx->l2tp_params.tlv.length = 1;

		ctx->l2tp_params.tlv.value =
@@ -1258,12 +1272,14 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type, 
		ctx = (struct ipa_hw_hdr_proc_ctx_remove_l2tp_hdr_cmd_seq *)

			(base + offset);

		ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;

		ctx->hdr_add.tlv.length = 1;

		ctx->hdr_add.tlv.length = is_64 ? 2 : 1;

		ctx->hdr_add.tlv.value = hdr_len;

		ctx->hdr_add.hdr_addr = is_hdr_proc_ctx ? phys_base :

		hdr_addr = is_hdr_proc_ctx ? phys_base :

			hdr_base_addr + offset_entry->offset;

		IPAHAL_DBG("header address 0x%llx length %d\n",

			ctx->hdr_add.hdr_addr, ctx->hdr_add.tlv.value);

			hdr_addr, ctx->hdr_add.tlv.value);

		IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,

			ctx->hdr_add.hdr_addr_hi, hdr_addr);

		ctx->l2tp_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD;

		ctx->l2tp_params.tlv.length = 1;

		ctx->l2tp_params.tlv.value =
@@ -1294,12 +1310,14 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type, 
		ctx = (struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq *)

			(base + offset);

		ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;

		ctx->hdr_add.tlv.length = 1;

		ctx->hdr_add.tlv.length = is_64 ? 2 : 1;

		ctx->hdr_add.tlv.value = hdr_len;

		ctx->hdr_add.hdr_addr = is_hdr_proc_ctx ? phys_base :

		hdr_addr = is_hdr_proc_ctx ? phys_base :

			hdr_base_addr + offset_entry->offset;

		IPAHAL_DBG("header address 0x%llx\n",

			ctx->hdr_add.hdr_addr);

			hdr_addr);

		IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,

			ctx->hdr_add.hdr_addr_hi, hdr_addr);

		ctx->cmd.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD;

		ctx->cmd.length = 0;

		switch (type) {
@@ -1357,7 +1375,8 @@ struct ipahal_hdr_funcs { 
			bool is_hdr_proc_ctx, dma_addr_t phys_base,

			u64 hdr_base_addr,

			struct ipa_hdr_offset_entry *offset_entry,

			struct ipa_l2tp_hdr_proc_ctx_params l2tp_params);

			struct ipa_l2tp_hdr_proc_ctx_params l2tp_params,

			bool is_64);



	int (*ipahal_get_proc_ctx_needed_len)(enum ipa_hdr_proc_type type);

};
@@ -1423,17 +1442,18 @@ void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *const hdr, 
 * @hdr_base_addr: base address in table

 * @offset_entry: offset from hdr_base_addr in table

 * @l2tp_params: l2tp parameters

 * @is_64: Indicates whether header base address/dma base address is 64 bit.

 */

int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,

		void *const base, u32 offset, u32 hdr_len,

		bool is_hdr_proc_ctx, dma_addr_t phys_base,

		u64 hdr_base_addr, struct ipa_hdr_offset_entry *offset_entry,

		struct ipa_l2tp_hdr_proc_ctx_params l2tp_params)

		struct ipa_l2tp_hdr_proc_ctx_params l2tp_params, bool is_64)

{

	IPAHAL_DBG(

		"type %d, base %pK, offset %d, hdr_len %d, is_hdr_proc_ctx %d, hdr_base_addr %llu, offset_entry %pK\n"

		"type %d, base %pK, offset %d, hdr_len %d, is_hdr_proc_ctx %d, hdr_base_addr %llu, offset_entry %pK, bool %d\n"

			, type, base, offset, hdr_len, is_hdr_proc_ctx,

			hdr_base_addr, offset_entry);

			hdr_base_addr, offset_entry, is_64);



	if (!base ||

		!hdr_len ||
@@ -1449,7 +1469,7 @@ int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type, 


	return hdr_funcs.ipahal_cp_proc_ctx_to_hw_buff(type, base, offset,

			hdr_len, is_hdr_proc_ctx, phys_base,

			hdr_base_addr, offset_entry, l2tp_params);

			hdr_base_addr, offset_entry, l2tp_params, is_64);

}



/*

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h

+2 −1
Original line number Diff line number Diff line
@@ -637,13 +637,14 @@ void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *hdr, u32 hdr_len); 
 * @hdr_base_addr: base address in table

 * @offset_entry: offset from hdr_base_addr in table

 * @l2tp_params: l2tp parameters

 * @is_64: Indicates whether header base address/dma base address is 64 bit.

 */

int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,

		void *base, u32 offset, u32 hdr_len,

		bool is_hdr_proc_ctx, dma_addr_t phys_base,

		u64 hdr_base_addr,

		struct ipa_hdr_offset_entry *offset_entry,

		struct ipa_l2tp_hdr_proc_ctx_params l2tp_params);

		struct ipa_l2tp_hdr_proc_ctx_params l2tp_params, bool is_64);



/*

 * ipahal_get_proc_ctx_needed_len() - calculates the needed length for addition

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_i.h

+2 −1
Original line number Diff line number Diff line
@@ -658,7 +658,8 @@ struct ipa_hw_hdr_proc_ctx_tlv { 
 */

struct ipa_hw_hdr_proc_ctx_hdr_add {

	struct ipa_hw_hdr_proc_ctx_tlv tlv;

	u64 hdr_addr;

	u32 hdr_addr;

	u32 hdr_addr_hi;

};



/**