Loading drivers/clk/qcom/clk-alpha-pll.c +2 −2 Original line number Diff line number Diff line Loading @@ -158,7 +158,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); /* LUCID PLL specific settings and offsets */ #define LUCID_PLL_CAL_VAL 0x44 #define LUCID_PCAL_DONE BIT(26) #define LUCID_PCAL_DONE BIT(27) /* ZONDA PLL specific offsets */ #define ZONDA_PLL_OUT_MASK 0x9 Loading Loading @@ -1720,7 +1720,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) int ret; /* Return early if calibration is not needed. */ regmap_read(pll->clkr.regmap, PLL_STATUS(pll), ®val); regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val); if (regval & LUCID_PCAL_DONE) return 0; Loading Loading
drivers/clk/qcom/clk-alpha-pll.c +2 −2 Original line number Diff line number Diff line Loading @@ -158,7 +158,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); /* LUCID PLL specific settings and offsets */ #define LUCID_PLL_CAL_VAL 0x44 #define LUCID_PCAL_DONE BIT(26) #define LUCID_PCAL_DONE BIT(27) /* ZONDA PLL specific offsets */ #define ZONDA_PLL_OUT_MASK 0x9 Loading Loading @@ -1720,7 +1720,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) int ret; /* Return early if calibration is not needed. */ regmap_read(pll->clkr.regmap, PLL_STATUS(pll), ®val); regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val); if (regval & LUCID_PCAL_DONE) return 0; Loading
