Commit 71d9c85b authored Jun 26, 2019 by David Dai

clk: qcom: clk-alpha-pll: check pcal_done from mode register

The sequence for alpha_pll_lucid_prepare is checking an incorrect bit
to determine whether or not a lucid PLL has calibrated successfully.
The bit in the status register is not observable unless pll_test_ctl[69]
is set and user_ctl[43:37] is 0 which should only be used as a fallback
option. Use the correct PCAL_DONE bit from the mode register to properly
determine PLL calibration status.

Change-Id: If952c30cacacd68c07e8d7dfd622069dbb70c909
Signed-off-by: David Dai <daidavid1@codeaurora.org>

parent 0ed7b350

drivers/clk/qcom/clk-alpha-pll.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -158,7 +158,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);

		/* LUCID PLL specific settings and offsets */
		#define LUCID_PLL_CAL_VAL 0x44
		#define LUCID_PCAL_DONE BIT(26)
		#define LUCID_PCAL_DONE BIT(27)

		/* ZONDA PLL specific offsets */
		#define ZONDA_PLL_OUT_MASK 0x9
		@@ -1720,7 +1720,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw)
		int ret;

		/* Return early if calibration is not needed. */
		regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);
		regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
		if (regval & LUCID_PCAL_DONE)
		return 0;