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Commit 058ca4a2 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2013-07-22' of... 

Merge tag 'drm-intel-fixes-2013-07-22' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes

- fixup panel fitter readout for gen2/3 (just quitens dmesg noise)
- fix pft computations for non-autoscaled resolutions (i.e. letter/pillar
  boxing on gen2/3)
- preserve the DDI A/E lane sharing bit (Stéphane Marchesin)
- fix the "rc6 fails to work after resume" regression, big thanks to
  Konstantin Khlebnikov for the patch and debug insight about what
  actually might be going on here
- fix Oops in is_crtc_connector_off (Chris)
- sanitize shared dpll state - our new paranoid state checker tripped up
  over dirt left behind by the BIOS
- correctly restore fences, fixes the "my screen is all messed up after
  resume" regression introduced in the final 3.10 pull request
- quirk backlights harder, this time for Dell XPS13 machines to fix a
  regression (patch from Kamal Mostafa)
- 90% fix for some haswell hangs when accessing registers concurrently,
  the 100% solution is simply too invasive for -fixes and what we have
  here seems to be good enough (Chris)

* tag 'drm-intel-fixes-2013-07-22' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915: fix up gt init sequence fallout
  drm/i915: Serialize almost all register access
  drm/i915: quirk no PCH_PWM_ENABLE for Dell XPS13 backlight
  drm/i915: correctly restore fences with objects attached
  drm/i915: Fix dereferencing invalid connectors in is_crtc_connector_off()
  drm/i915: Sanitize shared dpll state
  drm/i915: fix long-standing SNB regression in power consumption after resume v2
  drm/i915: Preserve the DDI_A_4_LANES bit from the bios
  drm/i915: fix pfit regression for non-autoscaled resolutions
  drm/i915: fix up readout of the lvds dither bit on gen2/3
parents 27ddabc3 181d1b9e

drivers/gpu/drm/i915/i915_dma.c

+9 −9
Original line number Diff line number Diff line
@@ -1495,6 +1495,14 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	dev_priv->dev = dev;

	dev_priv->info = info;



	spin_lock_init(&dev_priv->irq_lock);

	spin_lock_init(&dev_priv->gpu_error.lock);

	spin_lock_init(&dev_priv->rps.lock);

	spin_lock_init(&dev_priv->backlight.lock);

	mutex_init(&dev_priv->dpio_lock);

	mutex_init(&dev_priv->rps.hw_lock);

	mutex_init(&dev_priv->modeset_restore_lock);



	i915_dump_device_info(dev_priv);



	if (i915_get_bridge_dev(dev)) {
@@ -1585,6 +1593,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	intel_detect_pch(dev);



	intel_irq_init(dev);

	intel_gt_sanitize(dev);

	intel_gt_init(dev);



	/* Try to make sure MCHBAR is enabled before poking at it */
@@ -1610,15 +1619,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	if (!IS_I945G(dev) && !IS_I945GM(dev))

		pci_enable_msi(dev->pdev);



	spin_lock_init(&dev_priv->irq_lock);

	spin_lock_init(&dev_priv->gpu_error.lock);

	spin_lock_init(&dev_priv->rps.lock);

	spin_lock_init(&dev_priv->backlight.lock);

	mutex_init(&dev_priv->dpio_lock);



	mutex_init(&dev_priv->rps.hw_lock);

	mutex_init(&dev_priv->modeset_restore_lock);



	dev_priv->num_plane = 1;

	if (IS_VALLEYVIEW(dev))

		dev_priv->num_plane = 2;

drivers/gpu/drm/i915/i915_drv.c

+8 −5
Original line number Diff line number Diff line
@@ -706,7 +706,7 @@ static int i915_drm_thaw(struct drm_device *dev) 
{

	int error = 0;



	intel_gt_reset(dev);

	intel_gt_sanitize(dev);



	if (drm_core_check_feature(dev, DRIVER_MODESET)) {

		mutex_lock(&dev->struct_mutex);
@@ -732,7 +732,7 @@ int i915_resume(struct drm_device *dev) 


	pci_set_master(dev->pdev);



	intel_gt_reset(dev);

	intel_gt_sanitize(dev);



	/*

	 * Platforms with opregion should have sane BIOS, older ones (gen3 and
@@ -1253,21 +1253,21 @@ hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) 


#define __i915_read(x, y) \

u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \

	unsigned long irqflags; \

	u##x val = 0; \

	spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \

	if (IS_GEN5(dev_priv->dev)) \

		ilk_dummy_write(dev_priv); \

	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \

		unsigned long irqflags; \

		spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \

		if (dev_priv->forcewake_count == 0) \

			dev_priv->gt.force_wake_get(dev_priv); \

		val = read##y(dev_priv->regs + reg); \

		if (dev_priv->forcewake_count == 0) \

			dev_priv->gt.force_wake_put(dev_priv); \

		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \

	} else { \

		val = read##y(dev_priv->regs + reg); \

	} \

	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \

	trace_i915_reg_rw(false, reg, val, sizeof(val)); \

	return val; \

}
@@ -1280,8 +1280,10 @@ __i915_read(64, q) 


#define __i915_write(x, y) \

void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \

	unsigned long irqflags; \

	u32 __fifo_ret = 0; \

	trace_i915_reg_rw(true, reg, val, sizeof(val)); \

	spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \

	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \

		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \

	} \
@@ -1293,6 +1295,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ 
		gen6_gt_check_fifodbg(dev_priv); \

	} \

	hsw_unclaimed_reg_check(dev_priv, reg); \

	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \

}

__i915_write(8, b)

__i915_write(16, w)

drivers/gpu/drm/i915/i915_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -555,6 +555,7 @@ enum intel_sbi_destination { 
#define QUIRK_PIPEA_FORCE (1<<0)

#define QUIRK_LVDS_SSC_DISABLE (1<<1)

#define QUIRK_INVERT_BRIGHTNESS (1<<2)

#define QUIRK_NO_PCH_PWM_ENABLE (1<<3)



struct intel_fbdev;

struct intel_fbc_work;
@@ -1583,7 +1584,7 @@ void i915_handle_error(struct drm_device *dev, bool wedged); 
extern void intel_irq_init(struct drm_device *dev);

extern void intel_hpd_init(struct drm_device *dev);

extern void intel_gt_init(struct drm_device *dev);

extern void intel_gt_reset(struct drm_device *dev);

extern void intel_gt_sanitize(struct drm_device *dev);



void i915_error_state_free(struct kref *error_ref);

drivers/gpu/drm/i915/i915_gem.c

+16 −2
Original line number Diff line number Diff line
@@ -2258,7 +2258,17 @@ void i915_gem_restore_fences(struct drm_device *dev) 


	for (i = 0; i < dev_priv->num_fence_regs; i++) {

		struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];

		i915_gem_write_fence(dev, i, reg->obj);



		/*

		 * Commit delayed tiling changes if we have an object still

		 * attached to the fence, otherwise just clear the fence.

		 */

		if (reg->obj) {

			i915_gem_object_update_fence(reg->obj, reg,

						     reg->obj->tiling_mode);

		} else {

			i915_gem_write_fence(dev, i, NULL);

		}

	}

}
@@ -2795,6 +2805,10 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg, 
	if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))

		mb();



	WARN(obj && (!obj->stride || !obj->tiling_mode),

	     "bogus fence setup with stride: 0x%x, tiling mode: %i\n",

	     obj->stride, obj->tiling_mode);



	switch (INTEL_INFO(dev)->gen) {

	case 7:

	case 6:
@@ -2836,6 +2850,7 @@ static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, 
		fence->obj = NULL;

		list_del_init(&fence->lru_list);

	}

	obj->fence_dirty = false;

}



static int
@@ -2965,7 +2980,6 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj) 
		return 0;



	i915_gem_object_update_fence(obj, reg, enable);

	obj->fence_dirty = false;



	return 0;

}

drivers/gpu/drm/i915/intel_ddi.c

+6 −4
Original line number Diff line number Diff line
@@ -301,7 +301,7 @@ static void intel_ddi_mode_set(struct drm_encoder *encoder, 
		struct intel_digital_port *intel_dig_port =

			enc_to_dig_port(encoder);



		intel_dp->DP = intel_dig_port->port_reversal |

		intel_dp->DP = intel_dig_port->saved_port_bits |

			       DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;

		intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
@@ -1109,7 +1109,8 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder) 
		 * enabling the port.

		 */

		I915_WRITE(DDI_BUF_CTL(port),

			   intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE);

			   intel_dig_port->saved_port_bits |

			   DDI_BUF_CTL_ENABLE);

	} else if (type == INTEL_OUTPUT_EDP) {

		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -1347,8 +1348,9 @@ void intel_ddi_init(struct drm_device *dev, enum port port) 
	intel_encoder->get_config = intel_ddi_get_config;



	intel_dig_port->port = port;

	intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &

					DDI_BUF_PORT_REVERSAL;

	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &

					  (DDI_BUF_PORT_REVERSAL |

					   DDI_A_4_LANES);

	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);



	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;