clk: qcom: add common clock framework support for 14nm DSI PHY

Model and configure 14nm DSI PHY PLL using upstream clock framework
APIs. Add changes to define and register vco, divider, mux clocks
as per common clock infrastructure.

Change-Id: Idc51070e2bb36d1a757d2714d2875a99901321a7
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>