clk: qcom: mdss: fix reg_read/reg_write callbacks for DSI 28nm PLL

Add support to handle the reg_write/reg_read callbacks of
divider and mux clocks for DSI 28nm PLL to work properly in
conjunction with the upstream clock framework. Return the stored
VCO clock rate at the beginning of VCO recalc_rate callback if
the VCO clock frequency is already calculated as part of VCO
set_rate callback.

Change-Id: Ic3604a638d41e0202ed41ea24366624118c92a76
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>