Loading arch/arm/boot/dts/qcom/msm8996-mdss-pll.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -28,6 +28,9 @@ clock-names = "iface_clk"; clock-rate = <0>; /* Memory region for passing dynamic refresh pll codes */ memory-region = <&dfps_data_mem>; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; Loading arch/arm/boot/dts/qcom/msm8996.dtsi +9 −2 Original line number Diff line number Diff line Loading @@ -191,8 +191,15 @@ reg = <0 0x88800000 0 0x5c00000>; }; cont_splash_mem: cont_splash_mem@82400000 { reg = <0 0x82400000 0 0x1c00000>; dfps_data_mem: dfps_data_mem@82400000 { compatible = "shared-dma-pool"; no-map; reg = <0 0x82400000 0 0x1000>; label = "dfps_data_mem"; }; cont_splash_mem: cont_splash_mem@82401000 { reg = <0 0x82401000 0 0x1c00000>; label = "cont_splash_mem"; }; }; Loading Loading
arch/arm/boot/dts/qcom/msm8996-mdss-pll.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -28,6 +28,9 @@ clock-names = "iface_clk"; clock-rate = <0>; /* Memory region for passing dynamic refresh pll codes */ memory-region = <&dfps_data_mem>; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; Loading
arch/arm/boot/dts/qcom/msm8996.dtsi +9 −2 Original line number Diff line number Diff line Loading @@ -191,8 +191,15 @@ reg = <0 0x88800000 0 0x5c00000>; }; cont_splash_mem: cont_splash_mem@82400000 { reg = <0 0x82400000 0 0x1c00000>; dfps_data_mem: dfps_data_mem@82400000 { compatible = "shared-dma-pool"; no-map; reg = <0 0x82400000 0 0x1000>; label = "dfps_data_mem"; }; cont_splash_mem: cont_splash_mem@82401000 { reg = <0 0x82401000 0 0x1c00000>; label = "cont_splash_mem"; }; }; Loading