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Commit fcba9145 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC platform updates (part 3) from Arnd Bergmann:
 "This is the third and smallest of the SoC specific updates.  Changes
  include:

   - SMP support for the Xilinx zynq platform
   - Smaller imx changes
   - LPAE support for mvebu
   - Moving the orion5x, kirkwood, dove and mvebu platforms to a common
     "mbus" driver for their internal devices.

  It would be good to get feedback on the location of the "mbus" driver.
  Since this is used on multiple platforms may potentially get shared
  with other architectures (powerpc and arm64), it was moved to
  drivers/bus/.  We expect other similar drivers to get moved to the
  same place in order to avoid creating more top-level directories under
  drivers/ or cluttering up the messy drivers/misc/ even more."

* tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits)
  ARM: imx: reset_controller may be disabled
  ARM: mvebu: Align the internal registers virtual base to support LPAE
  ARM: mvebu: Limit the DMA zone when LPAE is selected
  arm: plat-orion: remove addr-map code
  arm: mach-mv78xx0: convert to use the mvebu-mbus driver
  arm: mach-orion5x: convert to use mvebu-mbus driver
  arm: mach-dove: convert to use mvebu-mbus driver
  arm: mach-kirkwood: convert to use mvebu-mbus driver
  arm: mach-mvebu: convert to use mvebu-mbus driver
  ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock
  ARM i.MX53: tve_di clock is not part of the CCM, but of TVE
  ARM i.MX53: make tve_ext_sel propagate rate change to PLL
  ARM i.MX53: Remove unused tve_gate clkdev entry
  ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree
  ARM: i.MX5: Add PATA and SRTC clocks
  ARM: imx: do not bring up unavailable cores
  ARM: imx: add initial imx6dl support
  ARM: imx1: mm: add call to mxc_device_init
  ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS
  ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS
  ...
parents a8c4b90e 5c5f0421

Documentation/devicetree/bindings/clock/imx5-clock.txt

+13 −1
Original line number Diff line number Diff line
@@ -38,7 +38,6 @@ clocks and IDs. 
	usb_phy_podf		23

	cpu_podf		24

	di_pred			25

	tve_di			26

	tve_s			27

	uart1_ipg_gate		28

	uart1_per_gate		29
@@ -172,6 +171,19 @@ clocks and IDs. 
	can1_serial_gate	157

	can1_ipg_gate		158

	owire_gate		159

	gpu3d_s			160

	gpu2d_s			161

	gpu3d_gate		162

	gpu2d_gate		163

	garb_gate		164

	cko1_sel		165

	cko1_podf		166

	cko1			167

	cko2_sel		168

	cko2_podf		169

	cko2			170

	srtc_gate		171

	pata_gate		172



Examples (for mx53):

Documentation/devicetree/bindings/clock/imx6q-clock.txt

+3 −0
Original line number Diff line number Diff line
@@ -205,6 +205,9 @@ clocks and IDs. 
	enet_ref		190

	usbphy1_gate		191

	usbphy2_gate		192

	pll4_post_div		193

	pll5_post_div		194

	pll5_video_div		195



Examples:

Documentation/devicetree/bindings/reset/fsl,imx-src.txt

0 → 100644
+49 −0
Original line number Diff line number Diff line 
Freescale i.MX System Reset Controller

======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: Should be "fsl,<chip>-src"

- reg: should be register base and length as documented in the

  datasheet

- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,

  in this order.

- #reset-cells: 1, see below



example:



src: src@020d8000 {

        compatible = "fsl,imx6q-src";

        reg = <0x020d8000 0x4000>;

        interrupts = <0 91 0x04 0 96 0x04>;

        #reset-cells = <1>;

};



Specifying reset lines connected to IP modules

==============================================



The system reset controller can be used to reset the GPU, VPU,

IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device

nodes should specify the reset line on the SRC in their resets

property, containing a phandle to the SRC device node and a

RESET_INDEX specifying which module to reset, as described in

reset.txt



example:



        ipu1: ipu@02400000 {

                resets = <&src 2>;

        };

        ipu2: ipu@02800000 {

                resets = <&src 4>;

        };



The following RESET_INDEX values are valid for i.MX5:

GPU_RESET     0

VPU_RESET     1

IPU1_RESET    2

OPEN_VG_RESET 3

The following additional RESET_INDEX value is valid for i.MX6:

IPU2_RESET    4

Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt

+3 −0
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@ Required properties: 
- interrupts: Should contain sync interrupt and error interrupt,

  in this order.

- #crtc-cells: 1, See below

- resets: phandle pointing to the system reset controller and

          reset line index, see reset/fsl,imx-src.txt for details



example:
@@ -16,6 +18,7 @@ ipu: ipu@18000000 { 
	compatible = "fsl,imx53-ipu";

	reg = <0x18000000 0x080000000>;

	interrupts = <11 10>;

	resets = <&src 2>;

};



Parallel display support

arch/arm/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -498,6 +498,7 @@ config ARCH_DOVE 
	select PINCTRL_DOVE

	select PLAT_ORION_LEGACY

	select USB_ARCH_HAS_EHCI

	select MVEBU_MBUS

	help

	  Support for the Marvell Dove SoC 88AP510
@@ -511,6 +512,7 @@ config ARCH_KIRKWOOD 
	select PINCTRL

	select PINCTRL_KIRKWOOD

	select PLAT_ORION_LEGACY

	select MVEBU_MBUS

	help

	  Support for the following Marvell Kirkwood series SoCs:

	  88F6180, 88F6192 and 88F6281.
@@ -522,6 +524,7 @@ config ARCH_MV78XX0 
	select GENERIC_CLOCKEVENTS

	select PCI

	select PLAT_ORION_LEGACY

	select MVEBU_MBUS

	help

	  Support for the following Marvell MV78xx0 series SoCs:

	  MV781x0, MV782x0.
@@ -534,6 +537,7 @@ config ARCH_ORION5X 
	select GENERIC_CLOCKEVENTS

	select PCI

	select PLAT_ORION_LEGACY

	select MVEBU_MBUS

	help

	  Support for the following Marvell Orion 5x series SoCs:

	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),