Merge "clk: msm: clock-gcc-8952: Set test-control values" (fbcfc0fd) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/clk/msm/clock-alpha-pll.c

+29 −13

Original line number	Original line	Diff line number	Diff line
	@@ -39,6 +39,8 @@
	#define USER_CTL_LO_REG(pll) (*pll->base + pll->offset + 0x10)		#define USER_CTL_LO_REG(pll) (*pll->base + pll->offset + 0x10)
	#define USER_CTL_HI_REG(pll) (*pll->base + pll->offset + 0x14)		#define USER_CTL_HI_REG(pll) (*pll->base + pll->offset + 0x14)
	#define CONFIG_CTL_REG(pll) (*pll->base + pll->offset + 0x18)		#define CONFIG_CTL_REG(pll) (*pll->base + pll->offset + 0x18)
			#define TEST_CTL_LO_REG(pll) (*pll->base + pll->offset + 0x1c)
			#define TEST_CTL_HI_REG(pll) (*pll->base + pll->offset + 0x20)

	#define PLL_BYPASSNL 0x2		#define PLL_BYPASSNL 0x2
	#define PLL_RESET_N 0x4		#define PLL_RESET_N 0x4
	@@ -691,6 +693,20 @@ void __init_alpha_pll(struct clk *c)
	writel_relaxed(regval, USER_CTL_HI_REG(pll));		writel_relaxed(regval, USER_CTL_HI_REG(pll));
	}		}

			if (masks->test_ctl_lo_mask) {
			regval = readl_relaxed(TEST_CTL_LO_REG(pll));
			regval &= ~masks->test_ctl_lo_mask;
			regval \|= pll->test_ctl_lo_val;
			writel_relaxed(regval, TEST_CTL_LO_REG(pll));
			}

			if (masks->test_ctl_hi_mask) {
			regval = readl_relaxed(TEST_CTL_HI_REG(pll));
			regval &= ~masks->test_ctl_hi_mask;
			regval \|= pll->test_ctl_hi_val;
			writel_relaxed(regval, TEST_CTL_HI_REG(pll));
			}

	if (pll->fsm_en_mask)		if (pll->fsm_en_mask)
	__set_fsm_mode(MODE_REG(pll));		__set_fsm_mode(MODE_REG(pll));

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -446,6 +446,8 @@ static struct alpha_pll_masks pll_masks_p = {
	.output_mask = 0xf,		.output_mask = 0xf,
	.update_mask = BIT(22),		.update_mask = BIT(22),
	.post_div_mask = BM(11, 8),		.post_div_mask = BM(11, 8),
			.test_ctl_lo_mask = BM(31, 0),
			.test_ctl_hi_mask = BM(31, 0),
	};		};

	/* Slewing plls won't allow to change vco_sel.		/* Slewing plls won't allow to change vco_sel.
	@@ -469,6 +471,8 @@ static struct alpha_pll_clk gpll3_clk_src = {
	*/		*/
	.post_div_config = 1 << 8,		.post_div_config = 1 << 8,
	.slew = true,		.slew = true,
			.config_ctl_val = 0x4001055b,
			.test_ctl_hi_val = 0x40000600,
	.c = {		.c = {
	.rate = 1050000000,		.rate = 1050000000,
	.parent = &xo_clk_src.c,		.parent = &xo_clk_src.c,

+5 −0

Original line number	Original line	Diff line number	Diff line
	@@ -27,6 +27,9 @@ struct alpha_pll_masks {
	u32 alpha_en_mask; /* alpha_en bit */		u32 alpha_en_mask; /* alpha_en bit */
	u32 output_mask; /* pllout_* bits */		u32 output_mask; /* pllout_* bits */
	u32 post_div_mask;		u32 post_div_mask;

			u32 test_ctl_lo_mask;
			u32 test_ctl_hi_mask;
	};		};

	struct alpha_pll_vco_tbl {		struct alpha_pll_vco_tbl {
	@@ -53,6 +56,8 @@ struct alpha_pll_clk {
	u32 enable_config; /* bitmask of outputs to be enabled */		u32 enable_config; /* bitmask of outputs to be enabled */
	u32 post_div_config; /* masked post divider setting */		u32 post_div_config; /* masked post divider setting */
	u32 config_ctl_val; /* config register init value */		u32 config_ctl_val; /* config register init value */
			u32 test_ctl_lo_val; /* test control settings */
			u32 test_ctl_hi_val;

	struct alpha_pll_vco_tbl *vco_tbl;		struct alpha_pll_vco_tbl *vco_tbl;
	u32 num_vco;		u32 num_vco;