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Commit 41fa7a12 authored by Arun KS's avatar Arun KS
Browse files

clk: msm: clock-gcc-8952: Set test-control values 



Hardware team requires setting of PLL test control and
config control registers. Add these to the pll structure.

Change-Id: I1578a7828dc6e7a0fe2dae7af1417d3f9df8cc75
Signed-off-by: default avatarArun KS <arunks@codeaurora.org>
parent 8609e262

drivers/clk/msm/clock-gcc-8952.c

+4 −0
Original line number Diff line number Diff line
@@ -446,6 +446,8 @@ static struct alpha_pll_masks pll_masks_p = { 
	.output_mask = 0xf,

	.update_mask = BIT(22),

	.post_div_mask = BM(11, 8),

	.test_ctl_lo_mask = BM(31, 0),

	.test_ctl_hi_mask = BM(31, 0),

};



/* Slewing plls won't allow to change vco_sel.
@@ -469,6 +471,8 @@ static struct alpha_pll_clk gpll3_clk_src = { 
	 */

	.post_div_config = 1 << 8,

	.slew = true,

	.config_ctl_val = 0x4001055b,

	.test_ctl_hi_val = 0x40000600,

	.c = {

		.rate = 1050000000,

		.parent = &xo_clk_src.c,