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Commit 8609e262 authored by Arun KS's avatar Arun KS
Browse files

clk: msm: clock-alpha-pll: Add test control programming



PLLs may require programming test control and config control
interfaces. Add support to program relevant registers.

Change-Id: Ib43237e59748da649f7757b97927faa7d650c8e8
Signed-off-by: default avatarArun KS <arunks@codeaurora.org>
parent cdecac51
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+29 −13
Original line number Diff line number Diff line
@@ -39,6 +39,8 @@
#define USER_CTL_LO_REG(pll)	(*pll->base + pll->offset + 0x10)
#define USER_CTL_HI_REG(pll)	(*pll->base + pll->offset + 0x14)
#define CONFIG_CTL_REG(pll)	(*pll->base + pll->offset + 0x18)
#define TEST_CTL_LO_REG(pll)	(*pll->base + pll->offset + 0x1c)
#define TEST_CTL_HI_REG(pll)	(*pll->base + pll->offset + 0x20)

#define PLL_BYPASSNL 0x2
#define PLL_RESET_N  0x4
@@ -690,6 +692,20 @@ void __init_alpha_pll(struct clk *c)
		writel_relaxed(regval, USER_CTL_HI_REG(pll));
	}

	if (masks->test_ctl_lo_mask) {
		regval = readl_relaxed(TEST_CTL_LO_REG(pll));
		regval &= ~masks->test_ctl_lo_mask;
		regval |= pll->test_ctl_lo_val;
		writel_relaxed(regval, TEST_CTL_LO_REG(pll));
	}

	if (masks->test_ctl_hi_mask) {
		regval = readl_relaxed(TEST_CTL_HI_REG(pll));
		regval &= ~masks->test_ctl_hi_mask;
		regval |= pll->test_ctl_hi_val;
		writel_relaxed(regval, TEST_CTL_HI_REG(pll));
	}

	if (pll->fsm_en_mask)
		__set_fsm_mode(MODE_REG(pll));

+5 −0
Original line number Diff line number Diff line
@@ -27,6 +27,9 @@ struct alpha_pll_masks {
	u32 alpha_en_mask;	/* alpha_en bit */
	u32 output_mask;	/* pllout_* bits */
	u32 post_div_mask;

	u32 test_ctl_lo_mask;
	u32 test_ctl_hi_mask;
};

struct alpha_pll_vco_tbl {
@@ -53,6 +56,8 @@ struct alpha_pll_clk {
	u32 enable_config;	/* bitmask of outputs to be enabled */
	u32 post_div_config;	/* masked post divider setting */
	u32 config_ctl_val;	/* config register init value */
	u32 test_ctl_lo_val;	/* test control settings */
	u32 test_ctl_hi_val;

	struct alpha_pll_vco_tbl *vco_tbl;
	u32 num_vco;