clk: mdss: Replace thulium with msm8996 in pll

			"qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909",

			"qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994",

			"qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992",

			"qcom,mdss_dsi_pll_thulium", "qcom,mdss_hdmi_pll_thulium"

			"qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996"

- cell-index:		Specifies the controller used

- reg:			offset and length of the register set for the device.

- reg-names :		names to refer to register sets related to this device

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28hpm.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28lpm.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-20nm.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-thulium.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-thulium-util.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996-util.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-edp-pll-28hpm.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-28hpm.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-20nm.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-thulium.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8996.o

#include "mdss-pll.h"

#include "mdss-dsi-pll.h"

#include "mdss-dsi-pll-thulium.h"

#include "mdss-dsi-pll-8996.h"

#define DSI_PLL_POLL_MAX_READS                  15

#define DSI_PLL_POLL_TIMEOUT_US                 1000

int set_mdss_byte_mux_sel_thulium(struct mux_clk *clk, int sel)

int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel)

{

	return 0;

}

int get_mdss_byte_mux_sel_thulium(struct mux_clk *clk)

int get_mdss_byte_mux_sel_8996(struct mux_clk *clk)

{

	return 0;

}

int set_mdss_pixel_mux_sel_thulium(struct mux_clk *clk, int sel)

int set_mdss_pixel_mux_sel_8996(struct mux_clk *clk, int sel)

{

	return 0;

}

int get_mdss_pixel_mux_sel_thulium(struct mux_clk *clk)

int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk)

{

	return 0;

}

	pr_debug("div=%d postdiv=%x n1div=%x\n",

			div, pout->pll_postdiv, pout->pll_n1div);

	/* registers commited at pll_db_commit_thulium() */

	/* registers commited at pll_db_commit_8996() */

	return 0;

}

	return n2div;

}

static bool pll_is_pll_locked_thulium(struct mdss_pll_resources *pll)

static bool pll_is_pll_locked_8996(struct mdss_pll_resources *pll)

{

	u32 status;

	bool pll_locked;

	return pll_locked;

}

static void dsi_pll_start_thulium(void __iomem *pll_base)

static void dsi_pll_start_8996(void __iomem *pll_base)

{

	pr_debug("start PLL at base=%p\n", pll_base);

	MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 1);

}

static void dsi_pll_stop_thulium(void __iomem *pll_base)

static void dsi_pll_stop_8996(void __iomem *pll_base)

{

	pr_debug("stop PLL at base=%p\n", pll_base);

	MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 0);

}

int dsi_pll_enable_seq_thulium(struct mdss_pll_resources *pll)

int dsi_pll_enable_seq_8996(struct mdss_pll_resources *pll)

{

	int rc = 0;

		return -EINVAL;

	}

	dsi_pll_start_thulium(pll->pll_base);

	dsi_pll_start_8996(pll->pll_base);

	/*

	 * both DSIPHY_PLL_CLKBUFLR_EN and DSIPHY_CMN_GLBL_TEST_CTRL

	 * enabled at mdss_dsi_thulium_phy_config()

	 * enabled at mdss_dsi_8996_phy_config()

	 */

	if (!pll_is_pll_locked_thulium(pll)) {

	if (!pll_is_pll_locked_8996(pll)) {

		pr_err("DSI PLL lock failed\n");

		rc = -EINVAL;

		goto init_lock_err;

	pll->handoff_resources = false;

	dsi_pll_stop_thulium(pll->pll_base);

	dsi_pll_stop_8996(pll->pll_base);

	/* stop pll output */

	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0);

	return;

}

static void mdss_dsi_pll_thulium_input_init(struct dsi_pll_db *pdb)

static void mdss_dsi_pll_8996_input_init(struct dsi_pll_db *pdb)

{

	pdb->in.fref = 19200000;	/* 19.2 Mhz*/

	pdb->in.fdata = 0;		/* bit clock rate */

	pdb->in.pll_r3ctrl = 1;		/* 1 */

}

static void pll_thulium_dec_frac_calc(struct dsi_pll_db *pdb,

static void pll_8996_dec_frac_calc(struct dsi_pll_db *pdb,

			 s64 vco_clk_rate, s64 fref)

{

	struct dsi_pll_input *pin = &pdb->in;

	pout->cmn_ldo_cntrl = 0x1c;

}

static u32 pll_thulium_kvco_slop(u32 vrate)

static u32 pll_8996_kvco_slop(u32 vrate)

{

	u32 slop = 0;

	return slop;

}

static void pll_thulium_calc_vco_count(struct dsi_pll_db *pdb,

static void pll_8996_calc_vco_count(struct dsi_pll_db *pdb,

			 s64 vco_clk_rate, s64 fref)

{

	struct dsi_pll_input *pin = &pdb->in;

	data -= 1;

	pout->pll_kvco_div_ref = data;

	cnt = pll_thulium_kvco_slop(vco_clk_rate);

	cnt = pll_8996_kvco_slop(vco_clk_rate);

	cnt *= 2;

	cnt /= 100;

	cnt *= pin->kvco_measure_time;

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_CRCTRL, data);

}

static void pll_db_commit_thulium(void __iomem *pll_base,

static void pll_db_commit_8996(void __iomem *pll_base,

					struct dsi_pll_db *pdb)

{

	struct dsi_pll_input *pin = &pdb->in;

	wmb();	/* make sure register committed */

}

int pll_vco_set_rate_thulium(struct clk *c, unsigned long rate)

int pll_vco_set_rate_8996(struct clk *c, unsigned long rate)

{

	int rc;

	struct dsi_pll_vco_clk *vco = to_vco_clk(c);

	pll->vco_current_rate = rate;

	pll->vco_ref_clk_rate = vco->ref_clk_rate;

	mdss_dsi_pll_thulium_input_init(pdb);

	mdss_dsi_pll_8996_input_init(pdb);

	pll_thulium_dec_frac_calc(pdb, pll->vco_current_rate,

	pll_8996_dec_frac_calc(pdb, pll->vco_current_rate,

					pll->vco_ref_clk_rate);

	pll_thulium_calc_vco_count(pdb, pll->vco_current_rate,

	pll_8996_calc_vco_count(pdb, pll->vco_current_rate,

					pll->vco_ref_clk_rate);

	/* commit slave if split display is enabled */

	slave = pll->slave;

	if (slave)

		pll_db_commit_thulium(slave->pll_base, pdb);

		pll_db_commit_8996(slave->pll_base, pdb);

	/* commit master itself */

	pll_db_commit_thulium(pll->pll_base, pdb);

	pll_db_commit_8996(pll->pll_base, pdb);

	mdss_pll_resource_enable(pll, false);

	return rc;

}

unsigned long pll_vco_get_rate_thulium(struct clk *c)

unsigned long pll_vco_get_rate_8996(struct clk *c)

{

	u64 vco_rate, multiplier = (1 << 20);

	s32 div_frac_start;

	return (unsigned long)vco_rate;

}

long pll_vco_round_rate_thulium(struct clk *c, unsigned long rate)

long pll_vco_round_rate_8996(struct clk *c, unsigned long rate)

{

	unsigned long rrate = rate;

	u32 div;

	return rrate;

}

enum handoff pll_vco_handoff_thulium(struct clk *c)

enum handoff pll_vco_handoff_8996(struct clk *c)

{

	int rc;

	enum handoff ret = HANDOFF_DISABLED_CLK;

		return ret;

	}

	if (pll_is_pll_locked_thulium(pll)) {

	if (pll_is_pll_locked_8996(pll)) {

		pll->handoff_resources = true;

		pll->pll_on = true;

		c->rate = pll_vco_get_rate_thulium(c);

		c->rate = pll_vco_get_rate_8996(c);

		ret = HANDOFF_ENABLED_CLK;

	} else {

		mdss_pll_resource_enable(pll, false);

	return ret;

}

int pll_vco_prepare_thulium(struct clk *c)

int pll_vco_prepare_8996(struct clk *c)

{

	int rc = 0;

	struct dsi_pll_vco_clk *vco = to_vco_clk(c);

	return rc;

}

void pll_vco_unprepare_thulium(struct clk *c)

void pll_vco_unprepare_8996(struct clk *c)

{

	struct dsi_pll_vco_clk *vco = to_vco_clk(c);

	struct mdss_pll_resources *pll = vco->priv;

#include <linux/clk/msm-clk.h>

#include <linux/workqueue.h>

#include <linux/clk/msm-clock-generic.h>

#include <dt-bindings/clock/msm-clocks-thulium.h>

#include <dt-bindings/clock/msm-clocks-8996.h>

#include "mdss-pll.h"

#include "mdss-dsi-pll.h"

#include "mdss-dsi-pll-thulium.h"

#include "mdss-dsi-pll-8996.h"

#define VCO_DELAY_USEC		1

/* Op structures */

static struct clk_ops clk_ops_dsi_vco = {

	.set_rate = pll_vco_set_rate_thulium,

	.round_rate = pll_vco_round_rate_thulium,

	.handoff = pll_vco_handoff_thulium,

	.prepare = pll_vco_prepare_thulium,

	.unprepare = pll_vco_unprepare_thulium,

	.set_rate = pll_vco_set_rate_8996,

	.round_rate = pll_vco_round_rate_8996,

	.handoff = pll_vco_handoff_8996,

	.prepare = pll_vco_prepare_8996,

	.unprepare = pll_vco_unprepare_8996,

};

static struct clk_div_ops post_n1_div_ops = {

};

static struct clk_mux_ops mdss_byte_mux_ops = {

	.set_mux_sel = set_mdss_byte_mux_sel_thulium,

	.get_mux_sel = get_mdss_byte_mux_sel_thulium,

	.set_mux_sel = set_mdss_byte_mux_sel_8996,

	.get_mux_sel = get_mdss_byte_mux_sel_8996,

};

static struct clk_mux_ops mdss_pixel_mux_ops = {

	.set_mux_sel = set_mdss_pixel_mux_sel_thulium,

	.get_mux_sel = get_mdss_pixel_mux_sel_thulium,

	.set_mux_sel = set_mdss_pixel_mux_sel_8996,

	.get_mux_sel = get_mdss_pixel_mux_sel_8996,

};

static struct dsi_pll_vco_clk dsi_vco_clk = {

	.min_rate = 1300000000,

	.max_rate = 2600000000,

	.pll_en_seq_cnt = 1,

	.pll_enable_seqs[0] = dsi_pll_enable_seq_thulium,

	.pll_enable_seqs[0] = dsi_pll_enable_seq_8996,

	.c = {

		.dbg_name = "dsi_vco_clk_thulium",

		.dbg_name = "dsi_vco_clk_8996",

		.ops = &clk_ops_dsi_vco,

		CLK_INIT(dsi_vco_clk.c),

	},

	}

};

static struct clk_lookup mdss_dsi_pllcc_thulium[] = {

static struct clk_lookup mdss_dsi_pllcc_8996[] = {

	CLK_LIST(mdss_byte_clk_mux),

	CLK_LIST(byte_clk_src),

	CLK_LIST(mdss_pixel_clk_mux),

	CLK_LIST(dsi_vco_clk),

};

int dsi_pll_clock_register_thulium(struct platform_device *pdev,

int dsi_pll_clock_register_8996(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res)

{

	int rc;

	clk_ops_gen_mux_dsi.round_rate = parent_round_rate;

	clk_ops_gen_mux_dsi.set_rate = parent_set_rate;

	if (pll_res->target_id == MDSS_PLL_TARGET_THULIUM) {

	if (pll_res->target_id == MDSS_PLL_TARGET_8996) {

		rc = of_msm_clock_register(pdev->dev.of_node,

				mdss_dsi_pllcc_thulium,

				ARRAY_SIZE(mdss_dsi_pllcc_thulium));

				mdss_dsi_pllcc_8996,

				ARRAY_SIZE(mdss_dsi_pllcc_8996));

		if (rc) {

			pr_err("Clock register failed\n");

			rc = -EPROBE_DEFER;

 * GNU General Public License for more details.

 */

#ifndef MDSS_DSI_PLL_THULIUM_H

#define MDSS_DSI_PLL_THULIUM_H

#ifndef MDSS_DSI_PLL_8996_H

#define MDSS_DSI_PLL_8996_H

#define DSIPHY_CMN_CLK_CFG0		0x0010

#define DSIPHY_CMN_CLK_CFG1		0x0014

	struct dsi_pll_output out;

};

int pll_vco_set_rate_thulium(struct clk *c, unsigned long rate);

long pll_vco_round_rate_thulium(struct clk *c, unsigned long rate);

enum handoff pll_vco_handoff_thulium(struct clk *c);

int pll_vco_prepare_thulium(struct clk *c);

void pll_vco_unprepare_thulium(struct clk *c);

int set_mdss_byte_mux_sel_thulium(struct mux_clk *clk, int sel);

int get_mdss_byte_mux_sel_thulium(struct mux_clk *clk);

int set_mdss_pixel_mux_sel_thulium(struct mux_clk *clk, int sel);

int get_mdss_pixel_mux_sel_thulium(struct mux_clk *clk);

int pll_vco_set_rate_8996(struct clk *c, unsigned long rate);

long pll_vco_round_rate_8996(struct clk *c, unsigned long rate);

enum handoff pll_vco_handoff_8996(struct clk *c);

int pll_vco_prepare_8996(struct clk *c);

void pll_vco_unprepare_8996(struct clk *c);

int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel);

int get_mdss_byte_mux_sel_8996(struct mux_clk *clk);

int set_mdss_pixel_mux_sel_8996(struct mux_clk *clk, int sel);

int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk);

int post_n1_div_set_div(struct div_clk *clk, int div);

int post_n1_div_get_div(struct div_clk *clk);

int n2_div_set_div(struct div_clk *clk, int div);

int n2_div_get_div(struct div_clk *clk);

int dsi_pll_enable_seq_thulium(struct mdss_pll_resources *pll);

int dsi_pll_enable_seq_8996(struct mdss_pll_resources *pll);

#endif  /* MDSS_DSI_PLL_THULIUM_H */

#endif  /* MDSS_DSI_PLL_8996_H */