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Commit f5128a0a authored by Veera Sundaram Sankaran's avatar Veera Sundaram Sankaran Committed by Matt Wagantall
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clk: mdss: Replace thulium with msm8996 in pll



Use appropriate SOC name.

Change-Id: I10b554129775e4b73e15ab173de7f8f3ef0a6b58
Signed-off-by: default avatarVeera Sundaram Sankaran <veeras@codeaurora.org>
parent 62d33941
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+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ Required properties:
			"qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909",
			"qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994",
			"qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992",
			"qcom,mdss_dsi_pll_thulium", "qcom,mdss_hdmi_pll_thulium"
			"qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996"
- cell-index:		Specifies the controller used
- reg:			offset and length of the register set for the device.
- reg-names :		names to refer to register sets related to this device
+3 −3
Original line number Diff line number Diff line
@@ -4,9 +4,9 @@ obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-util.o mdss-dsi-20nm-pll-util.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28hpm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28lpm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-20nm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-thulium.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-thulium-util.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996-util.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-edp-pll-28hpm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-28hpm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-20nm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-thulium.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8996.o
+33 −33
Original line number Diff line number Diff line
@@ -20,27 +20,27 @@

#include "mdss-pll.h"
#include "mdss-dsi-pll.h"
#include "mdss-dsi-pll-thulium.h"
#include "mdss-dsi-pll-8996.h"

#define DSI_PLL_POLL_MAX_READS                  15
#define DSI_PLL_POLL_TIMEOUT_US                 1000

int set_mdss_byte_mux_sel_thulium(struct mux_clk *clk, int sel)
int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel)
{
	return 0;
}

int get_mdss_byte_mux_sel_thulium(struct mux_clk *clk)
int get_mdss_byte_mux_sel_8996(struct mux_clk *clk)
{
	return 0;
}

int set_mdss_pixel_mux_sel_thulium(struct mux_clk *clk, int sel)
int set_mdss_pixel_mux_sel_8996(struct mux_clk *clk, int sel)
{
	return 0;
}

int get_mdss_pixel_mux_sel_thulium(struct mux_clk *clk)
int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk)
{
	return 0;
}
@@ -70,7 +70,7 @@ int post_n1_div_set_div(struct div_clk *clk, int div)
	pr_debug("div=%d postdiv=%x n1div=%x\n",
			div, pout->pll_postdiv, pout->pll_n1div);

	/* registers commited at pll_db_commit_thulium() */
	/* registers commited at pll_db_commit_8996() */

	return 0;
}
@@ -165,7 +165,7 @@ int n2_div_get_div(struct div_clk *clk)
	return n2div;
}

static bool pll_is_pll_locked_thulium(struct mdss_pll_resources *pll)
static bool pll_is_pll_locked_8996(struct mdss_pll_resources *pll)
{
	u32 status;
	bool pll_locked;
@@ -194,21 +194,21 @@ static bool pll_is_pll_locked_thulium(struct mdss_pll_resources *pll)
	return pll_locked;
}

static void dsi_pll_start_thulium(void __iomem *pll_base)
static void dsi_pll_start_8996(void __iomem *pll_base)
{
	pr_debug("start PLL at base=%p\n", pll_base);

	MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 1);
}

static void dsi_pll_stop_thulium(void __iomem *pll_base)
static void dsi_pll_stop_8996(void __iomem *pll_base)
{
	pr_debug("stop PLL at base=%p\n", pll_base);

	MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 0);
}

int dsi_pll_enable_seq_thulium(struct mdss_pll_resources *pll)
int dsi_pll_enable_seq_8996(struct mdss_pll_resources *pll)
{
	int rc = 0;

@@ -217,14 +217,14 @@ int dsi_pll_enable_seq_thulium(struct mdss_pll_resources *pll)
		return -EINVAL;
	}

	dsi_pll_start_thulium(pll->pll_base);
	dsi_pll_start_8996(pll->pll_base);

	/*
	 * both DSIPHY_PLL_CLKBUFLR_EN and DSIPHY_CMN_GLBL_TEST_CTRL
	 * enabled at mdss_dsi_thulium_phy_config()
	 * enabled at mdss_dsi_8996_phy_config()
	 */

	if (!pll_is_pll_locked_thulium(pll)) {
	if (!pll_is_pll_locked_8996(pll)) {
		pr_err("DSI PLL lock failed\n");
		rc = -EINVAL;
		goto init_lock_err;
@@ -280,7 +280,7 @@ static void dsi_pll_disable(struct clk *c)

	pll->handoff_resources = false;

	dsi_pll_stop_thulium(pll->pll_base);
	dsi_pll_stop_8996(pll->pll_base);

	/* stop pll output */
	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0);
@@ -296,7 +296,7 @@ static void dsi_pll_disable(struct clk *c)
	return;
}

static void mdss_dsi_pll_thulium_input_init(struct dsi_pll_db *pdb)
static void mdss_dsi_pll_8996_input_init(struct dsi_pll_db *pdb)
{
	pdb->in.fref = 19200000;	/* 19.2 Mhz*/
	pdb->in.fdata = 0;		/* bit clock rate */
@@ -335,7 +335,7 @@ static void mdss_dsi_pll_thulium_input_init(struct dsi_pll_db *pdb)
	pdb->in.pll_r3ctrl = 1;		/* 1 */
}

static void pll_thulium_dec_frac_calc(struct dsi_pll_db *pdb,
static void pll_8996_dec_frac_calc(struct dsi_pll_db *pdb,
			 s64 vco_clk_rate, s64 fref)
{
	struct dsi_pll_input *pin = &pdb->in;
@@ -374,7 +374,7 @@ static void pll_thulium_dec_frac_calc(struct dsi_pll_db *pdb,
	pout->cmn_ldo_cntrl = 0x1c;
}

static u32 pll_thulium_kvco_slop(u32 vrate)
static u32 pll_8996_kvco_slop(u32 vrate)
{
	u32 slop = 0;

@@ -388,7 +388,7 @@ static u32 pll_thulium_kvco_slop(u32 vrate)
	return slop;
}

static void pll_thulium_calc_vco_count(struct dsi_pll_db *pdb,
static void pll_8996_calc_vco_count(struct dsi_pll_db *pdb,
			 s64 vco_clk_rate, s64 fref)
{
	struct dsi_pll_input *pin = &pdb->in;
@@ -413,7 +413,7 @@ static void pll_thulium_calc_vco_count(struct dsi_pll_db *pdb,
	data -= 1;
	pout->pll_kvco_div_ref = data;

	cnt = pll_thulium_kvco_slop(vco_clk_rate);
	cnt = pll_8996_kvco_slop(vco_clk_rate);
	cnt *= 2;
	cnt /= 100;
	cnt *= pin->kvco_measure_time;
@@ -494,7 +494,7 @@ static void pll_db_commit_common(void __iomem *pll_base,
	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_CRCTRL, data);
}

static void pll_db_commit_thulium(void __iomem *pll_base,
static void pll_db_commit_8996(void __iomem *pll_base,
					struct dsi_pll_db *pdb)
{
	struct dsi_pll_input *pin = &pdb->in;
@@ -581,7 +581,7 @@ static void pll_db_commit_thulium(void __iomem *pll_base,
	wmb();	/* make sure register committed */
}

int pll_vco_set_rate_thulium(struct clk *c, unsigned long rate)
int pll_vco_set_rate_8996(struct clk *c, unsigned long rate)
{
	int rc;
	struct dsi_pll_vco_clk *vco = to_vco_clk(c);
@@ -606,28 +606,28 @@ int pll_vco_set_rate_thulium(struct clk *c, unsigned long rate)
	pll->vco_current_rate = rate;
	pll->vco_ref_clk_rate = vco->ref_clk_rate;

	mdss_dsi_pll_thulium_input_init(pdb);
	mdss_dsi_pll_8996_input_init(pdb);

	pll_thulium_dec_frac_calc(pdb, pll->vco_current_rate,
	pll_8996_dec_frac_calc(pdb, pll->vco_current_rate,
					pll->vco_ref_clk_rate);

	pll_thulium_calc_vco_count(pdb, pll->vco_current_rate,
	pll_8996_calc_vco_count(pdb, pll->vco_current_rate,
					pll->vco_ref_clk_rate);

	/* commit slave if split display is enabled */
	slave = pll->slave;
	if (slave)
		pll_db_commit_thulium(slave->pll_base, pdb);
		pll_db_commit_8996(slave->pll_base, pdb);

	/* commit master itself */
	pll_db_commit_thulium(pll->pll_base, pdb);
	pll_db_commit_8996(pll->pll_base, pdb);

	mdss_pll_resource_enable(pll, false);

	return rc;
}

unsigned long pll_vco_get_rate_thulium(struct clk *c)
unsigned long pll_vco_get_rate_8996(struct clk *c)
{
	u64 vco_rate, multiplier = (1 << 20);
	s32 div_frac_start;
@@ -669,7 +669,7 @@ unsigned long pll_vco_get_rate_thulium(struct clk *c)
	return (unsigned long)vco_rate;
}

long pll_vco_round_rate_thulium(struct clk *c, unsigned long rate)
long pll_vco_round_rate_8996(struct clk *c, unsigned long rate)
{
	unsigned long rrate = rate;
	u32 div;
@@ -690,7 +690,7 @@ long pll_vco_round_rate_thulium(struct clk *c, unsigned long rate)
	return rrate;
}

enum handoff pll_vco_handoff_thulium(struct clk *c)
enum handoff pll_vco_handoff_8996(struct clk *c)
{
	int rc;
	enum handoff ret = HANDOFF_DISABLED_CLK;
@@ -706,10 +706,10 @@ enum handoff pll_vco_handoff_thulium(struct clk *c)
		return ret;
	}

	if (pll_is_pll_locked_thulium(pll)) {
	if (pll_is_pll_locked_8996(pll)) {
		pll->handoff_resources = true;
		pll->pll_on = true;
		c->rate = pll_vco_get_rate_thulium(c);
		c->rate = pll_vco_get_rate_8996(c);
		ret = HANDOFF_ENABLED_CLK;
	} else {
		mdss_pll_resource_enable(pll, false);
@@ -718,7 +718,7 @@ enum handoff pll_vco_handoff_thulium(struct clk *c)
	return ret;
}

int pll_vco_prepare_thulium(struct clk *c)
int pll_vco_prepare_8996(struct clk *c)
{
	int rc = 0;
	struct dsi_pll_vco_clk *vco = to_vco_clk(c);
@@ -744,7 +744,7 @@ error:
	return rc;
}

void pll_vco_unprepare_thulium(struct clk *c)
void pll_vco_unprepare_8996(struct clk *c)
{
	struct dsi_pll_vco_clk *vco = to_vco_clk(c);
	struct mdss_pll_resources *pll = vco->priv;
+18 −18
Original line number Diff line number Diff line
@@ -20,11 +20,11 @@
#include <linux/clk/msm-clk.h>
#include <linux/workqueue.h>
#include <linux/clk/msm-clock-generic.h>
#include <dt-bindings/clock/msm-clocks-thulium.h>
#include <dt-bindings/clock/msm-clocks-8996.h>

#include "mdss-pll.h"
#include "mdss-dsi-pll.h"
#include "mdss-dsi-pll-thulium.h"
#include "mdss-dsi-pll-8996.h"

#define VCO_DELAY_USEC		1

@@ -38,11 +38,11 @@ static struct clk_ops clk_ops_gen_mux_dsi;

/* Op structures */
static struct clk_ops clk_ops_dsi_vco = {
	.set_rate = pll_vco_set_rate_thulium,
	.round_rate = pll_vco_round_rate_thulium,
	.handoff = pll_vco_handoff_thulium,
	.prepare = pll_vco_prepare_thulium,
	.unprepare = pll_vco_unprepare_thulium,
	.set_rate = pll_vco_set_rate_8996,
	.round_rate = pll_vco_round_rate_8996,
	.handoff = pll_vco_handoff_8996,
	.prepare = pll_vco_prepare_8996,
	.unprepare = pll_vco_unprepare_8996,
};

static struct clk_div_ops post_n1_div_ops = {
@@ -56,13 +56,13 @@ static struct clk_div_ops n2_div_ops = { /* hr_oclk3 */
};

static struct clk_mux_ops mdss_byte_mux_ops = {
	.set_mux_sel = set_mdss_byte_mux_sel_thulium,
	.get_mux_sel = get_mdss_byte_mux_sel_thulium,
	.set_mux_sel = set_mdss_byte_mux_sel_8996,
	.get_mux_sel = get_mdss_byte_mux_sel_8996,
};

static struct clk_mux_ops mdss_pixel_mux_ops = {
	.set_mux_sel = set_mdss_pixel_mux_sel_thulium,
	.get_mux_sel = get_mdss_pixel_mux_sel_thulium,
	.set_mux_sel = set_mdss_pixel_mux_sel_8996,
	.get_mux_sel = get_mdss_pixel_mux_sel_8996,
};

static struct dsi_pll_vco_clk dsi_vco_clk = {
@@ -70,9 +70,9 @@ static struct dsi_pll_vco_clk dsi_vco_clk = {
	.min_rate = 1300000000,
	.max_rate = 2600000000,
	.pll_en_seq_cnt = 1,
	.pll_enable_seqs[0] = dsi_pll_enable_seq_thulium,
	.pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
	.c = {
		.dbg_name = "dsi_vco_clk_thulium",
		.dbg_name = "dsi_vco_clk_8996",
		.ops = &clk_ops_dsi_vco,
		CLK_INIT(dsi_vco_clk.c),
	},
@@ -165,7 +165,7 @@ static struct mux_clk mdss_byte_clk_mux = {
	}
};

static struct clk_lookup mdss_dsi_pllcc_thulium[] = {
static struct clk_lookup mdss_dsi_pllcc_8996[] = {
	CLK_LIST(mdss_byte_clk_mux),
	CLK_LIST(byte_clk_src),
	CLK_LIST(mdss_pixel_clk_mux),
@@ -175,7 +175,7 @@ static struct clk_lookup mdss_dsi_pllcc_thulium[] = {
	CLK_LIST(dsi_vco_clk),
};

int dsi_pll_clock_register_thulium(struct platform_device *pdev,
int dsi_pll_clock_register_8996(struct platform_device *pdev,
				struct mdss_pll_resources *pll_res)
{
	int rc;
@@ -237,10 +237,10 @@ int dsi_pll_clock_register_thulium(struct platform_device *pdev,
	clk_ops_gen_mux_dsi.round_rate = parent_round_rate;
	clk_ops_gen_mux_dsi.set_rate = parent_set_rate;

	if (pll_res->target_id == MDSS_PLL_TARGET_THULIUM) {
	if (pll_res->target_id == MDSS_PLL_TARGET_8996) {
		rc = of_msm_clock_register(pdev->dev.of_node,
				mdss_dsi_pllcc_thulium,
				ARRAY_SIZE(mdss_dsi_pllcc_thulium));
				mdss_dsi_pllcc_8996,
				ARRAY_SIZE(mdss_dsi_pllcc_8996));
		if (rc) {
			pr_err("Clock register failed\n");
			rc = -EPROBE_DEFER;
+13 −13
Original line number Diff line number Diff line
@@ -10,8 +10,8 @@
 * GNU General Public License for more details.
 */

#ifndef MDSS_DSI_PLL_THULIUM_H
#define MDSS_DSI_PLL_THULIUM_H
#ifndef MDSS_DSI_PLL_8996_H
#define MDSS_DSI_PLL_8996_H

#define DSIPHY_CMN_CLK_CFG0		0x0010
#define DSIPHY_CMN_CLK_CFG1		0x0014
@@ -144,19 +144,19 @@ struct dsi_pll_db {
	struct dsi_pll_output out;
};

int pll_vco_set_rate_thulium(struct clk *c, unsigned long rate);
long pll_vco_round_rate_thulium(struct clk *c, unsigned long rate);
enum handoff pll_vco_handoff_thulium(struct clk *c);
int pll_vco_prepare_thulium(struct clk *c);
void pll_vco_unprepare_thulium(struct clk *c);
int set_mdss_byte_mux_sel_thulium(struct mux_clk *clk, int sel);
int get_mdss_byte_mux_sel_thulium(struct mux_clk *clk);
int set_mdss_pixel_mux_sel_thulium(struct mux_clk *clk, int sel);
int get_mdss_pixel_mux_sel_thulium(struct mux_clk *clk);
int pll_vco_set_rate_8996(struct clk *c, unsigned long rate);
long pll_vco_round_rate_8996(struct clk *c, unsigned long rate);
enum handoff pll_vco_handoff_8996(struct clk *c);
int pll_vco_prepare_8996(struct clk *c);
void pll_vco_unprepare_8996(struct clk *c);
int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel);
int get_mdss_byte_mux_sel_8996(struct mux_clk *clk);
int set_mdss_pixel_mux_sel_8996(struct mux_clk *clk, int sel);
int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk);
int post_n1_div_set_div(struct div_clk *clk, int div);
int post_n1_div_get_div(struct div_clk *clk);
int n2_div_set_div(struct div_clk *clk, int div);
int n2_div_get_div(struct div_clk *clk);
int dsi_pll_enable_seq_thulium(struct mdss_pll_resources *pll);
int dsi_pll_enable_seq_8996(struct mdss_pll_resources *pll);

#endif  /* MDSS_DSI_PLL_THULIUM_H */
#endif  /* MDSS_DSI_PLL_8996_H */
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