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Commit 62d33941 authored by Casey Piper's avatar Casey Piper Committed by Matt Wagantall
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clk: mdss: write lane mode when powering on HDMI PHY 



To improve the timing margin, lane mode selection
needs to be written during the HDMI PHY startup
sequence. This prevents a timing failure when
VDDCX or VCCA_CORE are applied rather than the
nominal value.

Change-Id: I2ed54f63903a473eca12fb4d8f3b542585397dae
Signed-off-by: default avatarCasey Piper <cpiper@codeaurora.org>
parent d0c6a5a9

drivers/clk/msm/mdss/mdss-hdmi-pll-thulium.c

+4 −0
Original line number Diff line number Diff line
@@ -762,6 +762,10 @@ static int hdmi_thulium_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk) 
				     QSERDES_TX_L0_CLKBUF_ENABLE, 0x03);

	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,

				     QSERDES_TX_L0_CLKBUF_ENABLE, 0x03);

	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET,

				     QSERDES_TX_L0_LANE_MODE, 0x03);

	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET,

				     QSERDES_TX_L0_LANE_MODE, 0x03);



	MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET,

		     QSERDES_TX_L0_TX_BAND, cfg.tx_l0_tx_band);