Loading arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi +8 −2 Original line number Original line Diff line number Diff line Loading @@ -69,7 +69,10 @@ gdsc_bimc_smmu: qcom,gdsc@c8ce020 { gdsc_bimc_smmu: qcom,gdsc@c8ce020 { compatible = "qcom,gdsc"; compatible = "qcom,gdsc"; regulator-name = "gdsc_bimc_smmu"; regulator-name = "gdsc_bimc_smmu"; reg = <0xc8ce020 0x4>; reg = <0xc8ce020 0x4>, <0xc8ce024 0x4>; reg-names = "base", "hw_ctrl_addr"; qcom,no-status-check-on-disable; status = "disabled"; status = "disabled"; }; }; Loading Loading @@ -133,7 +136,10 @@ gdsc_gpu_cx: qcom,gdsc@5066004 { gdsc_gpu_cx: qcom,gdsc@5066004 { compatible = "qcom,gdsc"; compatible = "qcom,gdsc"; regulator-name = "gdsc_gpu_cx"; regulator-name = "gdsc_gpu_cx"; reg = <0x5066004 0x4>; reg = <0x5066004 0x4>, <0x5066008 0x4>; reg-names = "base", "hw_ctrl_addr"; qcom,no-status-check-on-disable; status = "disabled"; status = "disabled"; }; }; Loading Loading
arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi +8 −2 Original line number Original line Diff line number Diff line Loading @@ -69,7 +69,10 @@ gdsc_bimc_smmu: qcom,gdsc@c8ce020 { gdsc_bimc_smmu: qcom,gdsc@c8ce020 { compatible = "qcom,gdsc"; compatible = "qcom,gdsc"; regulator-name = "gdsc_bimc_smmu"; regulator-name = "gdsc_bimc_smmu"; reg = <0xc8ce020 0x4>; reg = <0xc8ce020 0x4>, <0xc8ce024 0x4>; reg-names = "base", "hw_ctrl_addr"; qcom,no-status-check-on-disable; status = "disabled"; status = "disabled"; }; }; Loading Loading @@ -133,7 +136,10 @@ gdsc_gpu_cx: qcom,gdsc@5066004 { gdsc_gpu_cx: qcom,gdsc@5066004 { compatible = "qcom,gdsc"; compatible = "qcom,gdsc"; regulator-name = "gdsc_gpu_cx"; regulator-name = "gdsc_gpu_cx"; reg = <0x5066004 0x4>; reg = <0x5066004 0x4>, <0x5066008 0x4>; reg-names = "base", "hw_ctrl_addr"; qcom,no-status-check-on-disable; status = "disabled"; status = "disabled"; }; }; Loading