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Commit 6eaac803 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

ARM: dts: msm: Add hw_ctrl_addr register support to votable GDSCs 



Read the GDS_HW_CTRL register to determine the votable GDSC
states.

Change-Id: I95d1014072f4ad9f33294dc245262f4ff9faa8e1
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 090e59ba

arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi

+8 −2
Original line number Diff line number Diff line
@@ -69,7 +69,10 @@ 
	gdsc_bimc_smmu: qcom,gdsc@c8ce020 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_bimc_smmu";

		reg = <0xc8ce020 0x4>;

		reg = <0xc8ce020 0x4>,

		      <0xc8ce024 0x4>;

		reg-names = "base", "hw_ctrl_addr";

		qcom,no-status-check-on-disable;

		status = "disabled";

	};
@@ -133,7 +136,10 @@ 
	gdsc_gpu_cx: qcom,gdsc@5066004 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_gpu_cx";

		reg = <0x5066004 0x4>;

		reg = <0x5066004 0x4>,

		      <0x5066008 0x4>;

		reg-names = "base", "hw_ctrl_addr";

		qcom,no-status-check-on-disable;

		status = "disabled";

	};