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Commit f1db3f7f authored by Satya Durga Srinivasu Prabhala's avatar Satya Durga Srinivasu Prabhala
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drivers: GICv3: Add isb() before mb() per GICv3 requirement 



commit 0df0dc1c ("drivers: GICv3: Add mb() after the read of the
IAR1_EL1 and other registers") added mb() for ICC_IAR1_EL1,
ICC_PMR_EL1 and ICC_SGI1R_EL1. But, as per the GICv3 requirement,
an "ISB" or other context synchronization operation must precede the
"DSB" to ensure visibility of System register writes.

Change-Id: I519530cb9c7008aacbad1319f9159887f599dc9b
CRs-Fixed: 1004222
Signed-off-by: default avatarSatya Durga Srinivasu Prabhala <satyap@codeaurora.org>
parent 22c4c57b

drivers/irqchip/irq-gic-v3.c

+3 −0
Original line number Diff line number Diff line
@@ -123,6 +123,7 @@ static u64 __maybe_unused gic_read_iar(void) 


	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));

	/* As per the architecture specification */

	isb();

	mb();

	return irqstat;

}
@@ -131,6 +132,7 @@ static void __maybe_unused gic_write_pmr(u64 val) 
{

	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));

	/* As per the architecture specification */

	isb();

	mb();

}
@@ -150,6 +152,7 @@ static void __maybe_unused gic_write_sgi1r(u64 val) 
{

	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));

	/* As per the architecture specification */

	isb();

	mb();

}