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Commit 0df0dc1c authored by Trilok Soni's avatar Trilok Soni
Browse files

drivers: GICv3: Add mb() after the read of the IAR1_EL1 and other registers 



As per the GICv3 architecture spec section "Observability
of GIC Register Accsses", architecture execution of the "DSB"
gurantees that last interrupt identifier read from ICC_IAR{0,1}_EL1
is observable by the top-level Distributor and by accesses from
any processor to the top-level Distributor.

Same comment goes for the ICC_PMR_EL1 and ICC_SGI1R_EL1 too.

CRs-Fixed: 960754
Change-Id: I9c7bcdee51f71d369e2a6f04faf7a22c3c1381bc
Signed-off-by: default avatarTrilok Soni <tsoni@codeaurora.org>
parent 5f1c64ce

drivers/irqchip/irq-gic-v3.c

+6 −0
Original line number Diff line number Diff line
@@ -122,12 +122,16 @@ static u64 __maybe_unused gic_read_iar(void) 
	u64 irqstat;



	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));

	/* As per the architecture specification */

	mb();

	return irqstat;

}



static void __maybe_unused gic_write_pmr(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));

	/* As per the architecture specification */

	mb();

}



static void __maybe_unused gic_write_ctlr(u64 val)
@@ -145,6 +149,8 @@ static void __maybe_unused gic_write_grpen1(u64 val) 
static void __maybe_unused gic_write_sgi1r(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));

	/* As per the architecture specification */

	mb();

}



static void gic_enable_sre(void)