Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit eff57c59 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: cpp: Add support for mmu prefetch and cds"

parents f8c460bc 0fa29314

Documentation/devicetree/bindings/media/video/msm-cpp.txt

+46 −0
Original line number Diff line number Diff line
@@ -20,6 +20,36 @@ Required properties: 
- qcom,clock-rates: clock rate in Hz.

- qcom,min-clock-rate: minimum clock rate in Hz, to be set to CPP hardware in

  case dynamic clock scaling based on prevalent streams need lower clock rate.

- qcom,cpp-fw-payload-info: Child node for cpp node having infomration on

  cpp firmware payload offsets. This is mandatory node.



Required properties of the child node:

- qcom,stripe-base = Base offset of stripes in cpp payload.

- qcom,plane-base = Base offset of planes in cpp payload.

- qcom,stripe-size = size of each stripe in payload.

- qcom,plane-size = size of each plane in payload.

- qcom,fe-ptr-off = offset from stripe base to fetch engine address

  location in payload.

- qcom,we-ptr-off = offset from stripe base to write engine address

  location in payload.



Optional properties of the child node:

- qcom,ref-fe-ptr-off =  offset from stripe base to reference fetch engine

  address location in payload.

- qcom,ref-we-ptr-off = offset from stripe base to reference write engine

  address location in payload.

- qcom,we-meta-ptr-off = offset from stripe base to metadata address

  location in payload.

- qcom,fe-mmu-pf-ptr-off = offset from plane base to fetch engine mmu prefetch

  address min location in payload.

- qcom,ref-fe-mmu-pf-ptr-off = offset from plane base to reference fetch engine

  mmu prefetch address min location in payload.

- qcom,we-mmu-pf-ptr-off = offset from plane base to write engine mmu prefetch

  address min location in payload.

- qcom,dup-we-mmu-pf-ptr-off = offset from plane base to duplicate write engine

   mmu prefetch address min location in payload.

- qcom,ref-we-mmu-pf-ptr-off =  offset from plane base to reference write engine

   mmu prefetch address min location in payload.



Optional properties:

- mmagic-vdd-supply: phandle to GDSC regulator controlling mmagic.
@@ -63,4 +93,20 @@ Example: 
		qcom,clock-rates = <0 0 0 0 465000000 0 0 465000000 0 0 0 0>;

		qcom,min-clock-rate = <320000000>;

		qcom,bus-master = <1>;

		qcom,cpp-fw-payload-info {

			qcom,stripe-base = <553>;

			qcom,plane-base = <481>;

			qcom,stripe-size = <61>;

			qcom,plane-size = <24>;

			qcom,fe-ptr-off = <11>;

			qcom,we-ptr-off = <23>;

			qcom,ref-fe-ptr-off = <17>;

			qcom,ref-we-ptr-off = <36>;

			qcom,we-meta-ptr-off = <42>;

			qcom,fe-mmu-pf-ptr-off = <6>;

			qcom,ref-fe-mmu-pf-ptr-off = <9>;

			qcom,we-mmu-pf-ptr-off = <12>;

			qcom,dup-we-mmu-pf-ptr-off = <17>;

			qcom,ref-we-mmu-pf-ptr-off = <22>;

		};

	};

arch/arm/boot/dts/qcom/msm8996-camera.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -582,6 +582,22 @@ 
		qcom,min-clock-rate = <320000000>;

		qcom,bus-master = <1>;

		status = "ok";

		qcom,cpp-fw-payload-info {

			qcom,stripe-base = <553>;

			qcom,plane-base = <481>;

			qcom,stripe-size = <61>;

			qcom,plane-size = <24>;

			qcom,fe-ptr-off = <11>;

			qcom,we-ptr-off = <23>;

			qcom,ref-fe-ptr-off = <17>;

			qcom,ref-we-ptr-off = <36>;

			qcom,we-meta-ptr-off = <42>;

			qcom,fe-mmu-pf-ptr-off = <6>;

			qcom,ref-fe-mmu-pf-ptr-off = <9>;

			qcom,we-mmu-pf-ptr-off = <12>;

			qcom,dup-we-mmu-pf-ptr-off = <17>;

			qcom,ref-we-mmu-pf-ptr-off = <22>;

		};

	};



	qcom,fd@aa4000 {

drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c

+232 −183
Original line number Diff line number Diff line
@@ -60,17 +60,6 @@ 
#define CPP_FW_VERSION_1_8_0	0x10080000

#define CPP_FW_VERSION_1_10_0	0x10100000



/* stripe information offsets in frame command */

#define STRIPE_BASE_FW_1_2_0	130

#define STRIPE_BASE_FW_1_4_0	140

#define STRIPE_BASE_FW_1_6_0	464

#define STRIPE_BASE_FW_1_8_0	493

#define STRIPE_BASE_FW_1_10_0	553





#define PLANE_BASE_FW_1_8_0	478

#define PLANE_BASE_FW_1_10_0	481



/* dump the frame command before writing to the hardware */

#define  MSM_CPP_DUMP_FRM_CMD 0
@@ -82,6 +71,22 @@ 
#define CPP_GDSCR_SW_COLLAPSE_DISABLE 0xFFFFFFFD

#define CPP_GDSCR_HW_CONTROL_ENABLE 0x2

#define CPP_GDSCR_HW_CONTROL_DISABLE 0x1

#define PAYLOAD_NUM_PLANES 3

#define TNR_MASK 0x4

#define UBWC_MASK 0x20

#define CDS_MASK 0x40

#define MMU_PF_MASK 0x80



#define CPP_DT_READ_U32_ERR(_dev, _key, _str, _ret, _out) { \

		_key = _str; \

		_ret = of_property_read_u32(_dev, _key, &_out); \

		if (_ret) \

			break; \

	}



#define CPP_DT_READ_U32(_dev, _str, _out) { \

		of_property_read_u32(_dev, _str, &_out); \

	}



static int msm_cpp_buffer_ops(struct cpp_device *cpp_dev,

	uint32_t buff_mgr_ops, struct msm_buf_mngr_info *buff_mgr_info);
@@ -189,27 +194,6 @@ struct msm_cpp_timer_t { 


struct msm_cpp_timer_t cpp_timer;



static int msm_cpp_is_tnr_enabled(struct cpp_device *cpp_dev,

	uint32_t *cpp_frame_msg)

{

	if (cpp_frame_msg && cpp_dev) {

		if (((cpp_dev->fw_version & 0xffff0000) ==

			CPP_FW_VERSION_1_8_0) &&

			((cpp_frame_msg[PLANE_BASE_FW_1_8_0] & 0x40) ||

			(cpp_frame_msg[PLANE_BASE_FW_1_8_0 + 5] & 0x40) ||

			(cpp_frame_msg[PLANE_BASE_FW_1_8_0 + 10] & 0x40))) {

			return 1;

		} else if (((cpp_dev->fw_version & 0xffff0000) ==

			CPP_FW_VERSION_1_10_0) &&

			((cpp_frame_msg[PLANE_BASE_FW_1_10_0] & 0x40) ||

			(cpp_frame_msg[PLANE_BASE_FW_1_10_0 + 24] & 0x40) ||

			(cpp_frame_msg[PLANE_BASE_FW_1_10_0 + 48] & 0x40))) {

			return 1;

		}

	}

	return 0;

}



static int msm_cpp_init_bandwidth_mgr(struct cpp_device *cpp_dev)

{

	int rc = 0;
@@ -871,90 +855,67 @@ static void cpp_get_clk_freq_tbl(struct clk *clk, struct cpp_hw_info *hw_info, 
	hw_info->freq_tbl_count = idx;

}



static void msm_cpp_calculate_stripe_base(struct cpp_device *cpp_dev)

{

	if ((cpp_dev->fw_version & 0xffff0000) ==

		CPP_FW_VERSION_1_2_0) {

		cpp_dev->stripe_base = STRIPE_BASE_FW_1_2_0;

		cpp_dev->stripe_info_offset = 12;

		cpp_dev->stripe_size = 27;

		cpp_dev->rd_pntr = 5;

		cpp_dev->wr_0_pntr = 11;

		cpp_dev->wr_1_pntr = 12;

		cpp_dev->wr_2_pntr = 13;

		cpp_dev->wr_3_pntr = 14;

		cpp_dev->rd_ref_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_ref_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_0_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_1_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_2_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_3_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

	} else if ((cpp_dev->fw_version & 0xffff0000) ==

		CPP_FW_VERSION_1_4_0) {

		cpp_dev->stripe_base = STRIPE_BASE_FW_1_4_0;

		cpp_dev->stripe_info_offset = 12;

		cpp_dev->stripe_size = 27;

		cpp_dev->rd_pntr = 5;

		cpp_dev->wr_0_pntr = 11;

		cpp_dev->wr_1_pntr = 12;

		cpp_dev->wr_2_pntr = 13;

		cpp_dev->wr_3_pntr = 14;

		cpp_dev->rd_ref_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_ref_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_0_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_1_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_2_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_3_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

	} else if ((cpp_dev->fw_version & 0xffff0000) ==

		CPP_FW_VERSION_1_6_0) {

		cpp_dev->stripe_base = STRIPE_BASE_FW_1_6_0;

		cpp_dev->stripe_info_offset = 12;

		cpp_dev->stripe_size = 27;

		cpp_dev->rd_pntr = 5;

		cpp_dev->wr_0_pntr = 11;

		cpp_dev->wr_1_pntr = 12;

		cpp_dev->wr_2_pntr = 13;

		cpp_dev->wr_3_pntr = 14;

		cpp_dev->rd_ref_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_ref_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_0_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_1_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_2_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_3_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

	} else if ((cpp_dev->fw_version & 0xffff0000) ==

		CPP_FW_VERSION_1_8_0) {

		cpp_dev->stripe_base = STRIPE_BASE_FW_1_8_0;

		cpp_dev->stripe_info_offset = 9;

		cpp_dev->stripe_size = 48;

		cpp_dev->rd_pntr = 8;

		cpp_dev->wr_0_pntr = 20;

		cpp_dev->wr_1_pntr = 21;

		cpp_dev->wr_2_pntr = 22;

		cpp_dev->wr_3_pntr = 23;

		cpp_dev->rd_ref_pntr = 14;

		cpp_dev->wr_ref_pntr = 30;

		cpp_dev->wr_0_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_1_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_2_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

		cpp_dev->wr_3_meta_data_wr_pntr = MSM_CPP_INVALID_OFFSET;

	} else if ((cpp_dev->fw_version & 0xffff0000) ==

		CPP_FW_VERSION_1_10_0) {

		cpp_dev->stripe_base = STRIPE_BASE_FW_1_10_0;

		cpp_dev->stripe_info_offset = 9;

		cpp_dev->stripe_size = 61;

		cpp_dev->rd_pntr = 11;

		cpp_dev->wr_0_pntr = 23;

		cpp_dev->wr_1_pntr = 24;

		cpp_dev->wr_2_pntr = 25;

		cpp_dev->wr_3_pntr = 26;

		cpp_dev->rd_ref_pntr = 17;

		cpp_dev->wr_ref_pntr = 36;

		cpp_dev->wr_0_meta_data_wr_pntr = 42;

		cpp_dev->wr_1_meta_data_wr_pntr = 43;

		cpp_dev->wr_2_meta_data_wr_pntr = 44;

		cpp_dev->wr_3_meta_data_wr_pntr = 45;

static int msm_cpp_read_payload_params_from_dt(struct cpp_device *cpp_dev)

{

	struct platform_device *pdev = cpp_dev->pdev;

	struct device_node *fw_info_node = NULL, *dev_node = NULL;

	char *key = "qcom,cpp-fw-payload-info";

	struct msm_cpp_payload_params *payload_params;

	int ret = 0;



	if (!pdev || !pdev->dev.of_node) {

		pr_err("%s: Invalid platform device/node\n", __func__);

		ret = -ENODEV;

		goto no_cpp_node;

	}

	return;



	dev_node = pdev->dev.of_node;

	fw_info_node = of_find_node_by_name(dev_node, key);

	if (!fw_info_node) {

		ret = -ENODEV;

		goto no_binding;

	}

	payload_params = &cpp_dev->payload_params;

	memset(payload_params, 0x0, sizeof(struct msm_cpp_payload_params));



	do {

		CPP_DT_READ_U32_ERR(fw_info_node, key, "qcom,stripe-base", ret,

			payload_params->stripe_base);

		CPP_DT_READ_U32_ERR(fw_info_node, key, "qcom,plane-base", ret,

			payload_params->plane_base);

		CPP_DT_READ_U32_ERR(fw_info_node, key, "qcom,stripe-size", ret,

			payload_params->stripe_size);

		CPP_DT_READ_U32_ERR(fw_info_node, key, "qcom,plane-size", ret,

			payload_params->plane_size);

		CPP_DT_READ_U32_ERR(fw_info_node, key, "qcom,fe-ptr-off", ret,

			payload_params->rd_pntr_off);

		CPP_DT_READ_U32_ERR(fw_info_node, key, "qcom,we-ptr-off", ret,

			payload_params->wr_0_pntr_off);



		CPP_DT_READ_U32(fw_info_node, "qcom,ref-fe-ptr-off",

			payload_params->rd_ref_pntr_off);

		CPP_DT_READ_U32(fw_info_node, "qcom,ref-we-ptr-off",

			payload_params->wr_ref_pntr_off);

		CPP_DT_READ_U32(fw_info_node, "qcom,we-meta-ptr-off",

			payload_params->wr_0_meta_data_wr_pntr_off);

		CPP_DT_READ_U32(fw_info_node, "qcom,fe-mmu-pf-ptr-off",

			payload_params->fe_mmu_pf_ptr_off);

		CPP_DT_READ_U32(fw_info_node, "qcom,ref-fe-mmu-pf-ptr-off",

			payload_params->ref_fe_mmu_pf_ptr_off);

		CPP_DT_READ_U32(fw_info_node, "qcom,we-mmu-pf-ptr-off",

			payload_params->we_mmu_pf_ptr_off);

		CPP_DT_READ_U32(fw_info_node, "qcom,dup-we-mmu-pf-ptr-off",

			payload_params->dup_we_mmu_pf_ptr_off);

		CPP_DT_READ_U32(fw_info_node, "qcom,ref-we-mmu-pf-ptr-off",

			payload_params->ref_we_mmu_pf_ptr_off);

	} while (0);



no_binding:

	if (ret)

		pr_err("%s: Error reading binding %s, ret %d\n",

			__func__, key, ret);

no_cpp_node:

	return ret;

}



static int cpp_init_hardware(struct cpp_device *cpp_dev)
@@ -1342,9 +1303,6 @@ static void cpp_load_fw(struct cpp_device *cpp_dev, char *fw_name_bin) 
	pr_info("CPP FW Version: 0x%08x\n", cpp_dev->fw_version);

	msm_cpp_poll(cpp_dev->base, MSM_CPP_MSG_ID_TRAILER);



	/* Update the payload offsets */

	msm_cpp_calculate_stripe_base(cpp_dev);



	/*Disable MC clock*/

	/*msm_camera_io_w(0x0, cpp_dev->base +

					   MSM_CPP_MICRO_CLKEN_CTL);*/
@@ -1652,13 +1610,15 @@ static int msm_cpp_dump_frame_cmd(struct msm_cpp_frame_info_t *frame_info) 


	CPP_DBG("msg[%03d] = 0x%08x\n", 0, 0x6);

	/* send top level and plane level */

	for (i = 0; i < cpp_dev->stripe_base; i++)

	for (i = 0; i < cpp_dev->payload_params.stripe_base; i++)

		CPP_DBG("msg[%03d] = 0x%08x\n", i,

			frame_info->cpp_cmd_msg[i]);

	/* send stripes */

	i1 = cpp_dev->stripe_base +

		cpp_dev->stripe_size * frame_info->first_stripe_index;

	i2 = cpp_dev->stripe_size * (frame_info->last_stripe_index -

	i1 = cpp_dev->payload_params.stripe_base +

		cpp_dev->payload_params.stripe_size *

		frame_info->first_stripe_index;

	i2 = cpp_dev->payload_params.stripe_size *

		(frame_info->last_stripe_index -

		frame_info->first_stripe_index + 1);

	for (i = 0; i < i2; i++)

		CPP_DBG("msg[%03d] = 0x%08x\n", i+i1,
@@ -1751,17 +1711,17 @@ static void msm_cpp_do_timeout_work(struct work_struct *work) 


		msm_cpp_write(0x6, cpp_dev->base);

		/* send top level and plane level */

		for (j = 0; j < cpp_dev->stripe_base; j++) {

		for (j = 0; j < cpp_dev->payload_params.stripe_base; j++) {

			if (j % MSM_CPP_RX_FIFO_LEVEL == 0)

				msm_cpp_poll_rx_empty(cpp_dev->base);

			msm_cpp_write(processed_frame[i]->cpp_cmd_msg[j],

				cpp_dev->base);

		}

		/* send stripes */

		i1 = cpp_dev->stripe_base +

			cpp_dev->stripe_size *

		i1 = cpp_dev->payload_params.stripe_base +

			cpp_dev->payload_params.stripe_size *

			processed_frame[i]->first_stripe_index;

		i2 = cpp_dev->stripe_size *

		i2 = cpp_dev->payload_params.stripe_size *

			(processed_frame[i]->last_stripe_index -

			processed_frame[i]->first_stripe_index + 1);

		for (j = 0; j < i2; j++) {
@@ -1823,16 +1783,18 @@ static int msm_cpp_send_frame_to_hardware(struct cpp_device *cpp_dev, 


		msm_cpp_write(0x6, cpp_dev->base);

		/* send top level and plane level */

		for (i = 0; i < cpp_dev->stripe_base; i++) {

		for (i = 0; i < cpp_dev->payload_params.stripe_base; i++) {

			if (i % MSM_CPP_RX_FIFO_LEVEL == 0)

				msm_cpp_poll_rx_empty(cpp_dev->base);

			msm_cpp_write(process_frame->cpp_cmd_msg[i],

				cpp_dev->base);

		}

		/* send stripes */

		i1 = cpp_dev->stripe_base + cpp_dev->stripe_size *

		i1 = cpp_dev->payload_params.stripe_base +

			cpp_dev->payload_params.stripe_size *

			process_frame->first_stripe_index;

		i2 = cpp_dev->stripe_size * (process_frame->last_stripe_index -

		i2 = cpp_dev->payload_params.stripe_size *

			(process_frame->last_stripe_index -

			process_frame->first_stripe_index + 1);

		for (i = 0; i < i2; i++) {

			if (i % MSM_CPP_RX_FIFO_LEVEL == 0)
@@ -1951,6 +1913,134 @@ static int msm_cpp_check_buf_type(struct msm_buf_mngr_info *buff_mgr_info, 


	return num_output_bufs;

}



static void msm_cpp_update_frame_msg_phy_address(struct cpp_device *cpp_dev,

	struct msm_cpp_frame_info_t *new_frame, unsigned long in_phyaddr,

	unsigned long out_phyaddr0, unsigned long out_phyaddr1,

	unsigned long tnr_scratch_buffer0, unsigned long tnr_scratch_buffer1)

{

	int32_t stripe_base, plane_base;

	uint32_t rd_pntr_off, wr_0_pntr_off, wr_1_pntr_off,

		wr_2_pntr_off, wr_3_pntr_off;

	uint32_t wr_0_meta_data_wr_pntr_off, wr_1_meta_data_wr_pntr_off,

		wr_2_meta_data_wr_pntr_off, wr_3_meta_data_wr_pntr_off;

	uint32_t rd_ref_pntr_off, wr_ref_pntr_off;

	uint32_t stripe_size, plane_size;

	uint32_t fe_mmu_pf_ptr_off, ref_fe_mmu_pf_ptr_off, we_mmu_pf_ptr_off,

		dup_we_mmu_pf_ptr_off, ref_we_mmu_pf_ptr_off;

	uint8_t tnr_enabled, ubwc_enabled, mmu_pf_en, cds_en;

	int32_t i = 0;

	uint32_t *cpp_frame_msg;



	cpp_frame_msg = new_frame->cpp_cmd_msg;



	/* Update stripe/plane size and base offsets */

	stripe_base = cpp_dev->payload_params.stripe_base;

	stripe_size = cpp_dev->payload_params.stripe_size;

	plane_base = cpp_dev->payload_params.plane_base;

	plane_size = cpp_dev->payload_params.plane_size;



	/* Fetch engine Offset */

	rd_pntr_off = cpp_dev->payload_params.rd_pntr_off;

	/* Write engine offsets */

	wr_0_pntr_off = cpp_dev->payload_params.wr_0_pntr_off;

	wr_1_pntr_off = wr_0_pntr_off + 1;

	wr_2_pntr_off = wr_1_pntr_off + 1;

	wr_3_pntr_off = wr_2_pntr_off + 1;

	/* Reference engine offsets */

	rd_ref_pntr_off = cpp_dev->payload_params.rd_ref_pntr_off;

	wr_ref_pntr_off = cpp_dev->payload_params.wr_ref_pntr_off;

	/* Meta data offsets */

	wr_0_meta_data_wr_pntr_off =

		cpp_dev->payload_params.wr_0_meta_data_wr_pntr_off;

	wr_1_meta_data_wr_pntr_off = (wr_0_meta_data_wr_pntr_off + 1);

	wr_2_meta_data_wr_pntr_off = (wr_1_meta_data_wr_pntr_off + 1);

	wr_3_meta_data_wr_pntr_off = (wr_2_meta_data_wr_pntr_off + 1);

	/* MMU PF offsets */

	fe_mmu_pf_ptr_off = cpp_dev->payload_params.fe_mmu_pf_ptr_off;

	ref_fe_mmu_pf_ptr_off = cpp_dev->payload_params.ref_fe_mmu_pf_ptr_off;

	we_mmu_pf_ptr_off = cpp_dev->payload_params.we_mmu_pf_ptr_off;

	dup_we_mmu_pf_ptr_off = cpp_dev->payload_params.dup_we_mmu_pf_ptr_off;

	ref_we_mmu_pf_ptr_off = cpp_dev->payload_params.ref_we_mmu_pf_ptr_off;



	pr_debug("%s: feature_mask 0x%x\n", __func__, new_frame->feature_mask);



	/* Update individual module status from feature mask */

	tnr_enabled = ((new_frame->feature_mask & TNR_MASK) >> 2);

	ubwc_enabled = ((new_frame->feature_mask & UBWC_MASK) >> 5);

	cds_en = ((new_frame->feature_mask & CDS_MASK) >> 6);

	mmu_pf_en = ((new_frame->feature_mask & MMU_PF_MASK) >> 7);



	/*

	 * Update the stripe based addresses for fetch/write/reference engines.

	 * Update meta data offset for ubwc.

	 * Update ref engine address for cds / tnr.

	 */

	for (i = 0; i < new_frame->num_strips; i++) {

		cpp_frame_msg[stripe_base + rd_pntr_off + i * stripe_size] +=

			(uint32_t) in_phyaddr;

		cpp_frame_msg[stripe_base + wr_0_pntr_off + i * stripe_size] +=

			(uint32_t) out_phyaddr0;

		cpp_frame_msg[stripe_base + wr_1_pntr_off + i * stripe_size] +=

			(uint32_t) out_phyaddr1;

		cpp_frame_msg[stripe_base + wr_2_pntr_off + i * stripe_size] +=

			(uint32_t) out_phyaddr0;

		cpp_frame_msg[stripe_base + wr_3_pntr_off + i * stripe_size] +=

			(uint32_t) out_phyaddr1;

		if (tnr_enabled) {

			cpp_frame_msg[stripe_base + rd_ref_pntr_off +

				i * stripe_size] +=

				(uint32_t)tnr_scratch_buffer0;

			cpp_frame_msg[stripe_base + wr_ref_pntr_off +

				i * stripe_size] +=

				(uint32_t)tnr_scratch_buffer1;

		} else if (cds_en) {

			cpp_frame_msg[stripe_base + rd_ref_pntr_off +

				i * stripe_size] +=

				(uint32_t)in_phyaddr;

		}

		if (ubwc_enabled) {

			cpp_frame_msg[stripe_base + wr_0_meta_data_wr_pntr_off +

				i * stripe_size] += (uint32_t) out_phyaddr0;

			cpp_frame_msg[stripe_base + wr_1_meta_data_wr_pntr_off +

				i * stripe_size] += (uint32_t) out_phyaddr1;

			cpp_frame_msg[stripe_base + wr_2_meta_data_wr_pntr_off +

				i * stripe_size] += (uint32_t) out_phyaddr0;

			cpp_frame_msg[stripe_base + wr_3_meta_data_wr_pntr_off +

				i * stripe_size] += (uint32_t) out_phyaddr1;

		}

	}



	if (!mmu_pf_en)

		goto exit;



	/* Update mmu prefetch related plane specific address */

	for (i = 0; i < PAYLOAD_NUM_PLANES; i++) {

		cpp_frame_msg[plane_base + fe_mmu_pf_ptr_off +

			i * plane_size] += (uint32_t)in_phyaddr;

		cpp_frame_msg[plane_base + fe_mmu_pf_ptr_off +

			i * plane_size + 1] += (uint32_t)in_phyaddr;

		cpp_frame_msg[plane_base + ref_fe_mmu_pf_ptr_off +

			i * plane_size] += (uint32_t)tnr_scratch_buffer0;

		cpp_frame_msg[plane_base + ref_fe_mmu_pf_ptr_off +

			i * plane_size + 1] += (uint32_t)tnr_scratch_buffer0;

		cpp_frame_msg[plane_base + we_mmu_pf_ptr_off +

			i * plane_size] += (uint32_t)out_phyaddr0;

		cpp_frame_msg[plane_base + we_mmu_pf_ptr_off +

			i * plane_size + 1] += (uint32_t)out_phyaddr0;

		cpp_frame_msg[plane_base + dup_we_mmu_pf_ptr_off +

			i * plane_size] += (uint32_t)out_phyaddr1;

		cpp_frame_msg[plane_base + dup_we_mmu_pf_ptr_off +

			i * plane_size + 1] += (uint32_t)out_phyaddr1;

		cpp_frame_msg[plane_base + ref_we_mmu_pf_ptr_off +

			i * plane_size] += (uint32_t)tnr_scratch_buffer1;

		cpp_frame_msg[plane_base + ref_we_mmu_pf_ptr_off +

			i * plane_size + 1] += (uint32_t)tnr_scratch_buffer1;

	}

exit:

	return;

}



static int msm_cpp_cfg_frame(struct cpp_device *cpp_dev,

	struct msm_cpp_frame_info_t *new_frame)

{
@@ -1965,35 +2055,20 @@ static int msm_cpp_cfg_frame(struct cpp_device *cpp_dev, 
	int32_t in_fd;

	int32_t i = 0, num_output_bufs = 1;

	int32_t stripe_base = 0;

	uint32_t rd_pntr, wr_0_pntr, wr_1_pntr, wr_2_pntr, wr_3_pntr;

	uint32_t wr_0_meta_data_wr_pntr, wr_1_meta_data_wr_pntr,

		wr_2_meta_data_wr_pntr, wr_3_meta_data_wr_pntr;

	uint32_t rd_ref_pntr, wr_ref_pntr, stripe_info_offset, stripe_size;

	uint8_t tnr_enabled, ubwc_enabled;

	uint32_t stripe_size;

	uint8_t tnr_enabled;

	enum msm_camera_buf_mngr_buf_type buf_type =

		MSM_CAMERA_BUF_MNGR_BUF_PLANAR;



	stripe_base = cpp_dev->payload_params.stripe_base;

	stripe_size = cpp_dev->payload_params.stripe_size;



	if (!new_frame) {

		pr_err("%s: Frame is Null\n", __func__);

		return -EINVAL;

	}

	cpp_frame_msg = new_frame->cpp_cmd_msg;



	stripe_base = cpp_dev->stripe_base;

	stripe_info_offset = cpp_dev->stripe_info_offset;

	stripe_size = cpp_dev->stripe_size;

	rd_pntr = cpp_dev->rd_pntr;

	wr_0_pntr = cpp_dev->wr_0_pntr;

	wr_1_pntr = cpp_dev->wr_1_pntr;

	wr_2_pntr = cpp_dev->wr_2_pntr;

	wr_3_pntr = cpp_dev->wr_3_pntr;

	rd_ref_pntr = cpp_dev->rd_ref_pntr;

	wr_ref_pntr = cpp_dev->wr_ref_pntr;

	wr_0_meta_data_wr_pntr = cpp_dev->wr_0_meta_data_wr_pntr;

	wr_1_meta_data_wr_pntr = cpp_dev->wr_1_meta_data_wr_pntr;

	wr_2_meta_data_wr_pntr = cpp_dev->wr_2_meta_data_wr_pntr;

	wr_3_meta_data_wr_pntr = cpp_dev->wr_3_meta_data_wr_pntr;



	if (cpp_frame_msg == NULL ||

		(new_frame->msg_len < MSM_CPP_MIN_FRAME_LENGTH)) {

		pr_err("Length is not correct or frame message is missing\n");
@@ -2168,9 +2243,7 @@ static int msm_cpp_cfg_frame(struct cpp_device *cpp_dev, 
		}

	}



	tnr_enabled = msm_cpp_is_tnr_enabled(cpp_dev, cpp_frame_msg);

	pr_debug("%s: feature_mask 0x%x\n", __func__, new_frame->feature_mask);

	ubwc_enabled = ((new_frame->feature_mask & 0x20) >> 5);

	tnr_enabled = ((new_frame->feature_mask & TNR_MASK) >> 2);

	if (tnr_enabled) {

		tnr_scratch_buffer0 = msm_cpp_fetch_buffer_info(cpp_dev,

			&new_frame->tnr_scratch_buffer_info[0],
@@ -2198,38 +2271,10 @@ static int msm_cpp_cfg_frame(struct cpp_device *cpp_dev, 
		tnr_scratch_buffer1 = 0;

	}



	for (i = 0; i < new_frame->num_strips; i++) {

		cpp_frame_msg[stripe_base + rd_pntr + i * stripe_size] +=

			(uint32_t) in_phyaddr;

		cpp_frame_msg[stripe_base + wr_0_pntr + i * stripe_size] +=

			(uint32_t) out_phyaddr0;

		cpp_frame_msg[stripe_base + wr_1_pntr + i * stripe_size] +=

			(uint32_t) out_phyaddr1;

		cpp_frame_msg[stripe_base + wr_2_pntr + i * stripe_size] +=

			(uint32_t) out_phyaddr0;

		cpp_frame_msg[stripe_base + wr_3_pntr + i * stripe_size] +=

			(uint32_t) out_phyaddr1;

		if (tnr_enabled) {

			cpp_frame_msg[stripe_base + rd_ref_pntr +

				i * stripe_size] +=

				(uint32_t)tnr_scratch_buffer0;

			cpp_frame_msg[stripe_base + wr_ref_pntr +

				i * stripe_size] +=

				(uint32_t)tnr_scratch_buffer1;

		}

		if (ubwc_enabled) {

			cpp_frame_msg[stripe_base + wr_0_meta_data_wr_pntr +

				i * stripe_size] += (uint32_t) out_phyaddr0;

			cpp_frame_msg[stripe_base + wr_1_meta_data_wr_pntr +

				i * stripe_size] += (uint32_t) out_phyaddr1;

			cpp_frame_msg[stripe_base + wr_2_meta_data_wr_pntr +

				i * stripe_size] += (uint32_t) out_phyaddr0;

			cpp_frame_msg[stripe_base + wr_3_meta_data_wr_pntr +

				i * stripe_size] += (uint32_t) out_phyaddr1;



		}

	}



	msm_cpp_update_frame_msg_phy_address(cpp_dev, new_frame,

		in_phyaddr, out_phyaddr0, out_phyaddr1,

		tnr_scratch_buffer0, tnr_scratch_buffer1);

	if (tnr_enabled) {

		cpp_frame_msg[10] = tnr_scratch_buffer1 -

			tnr_scratch_buffer0;
@@ -3645,6 +3690,10 @@ static int cpp_probe(struct platform_device *pdev) 
	if (rc)

		cpp_dev->bus_master_flag = 0;



	rc = msm_cpp_read_payload_params_from_dt(cpp_dev);

	if (rc)

		goto cpp_probe_init_error;



	rc = cpp_init_hardware(cpp_dev);

	if (rc < 0)

		goto cpp_probe_init_error;

drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.h

+20 −14
Original line number Diff line number Diff line
@@ -175,6 +175,25 @@ struct msm_cpp_work_t { 
	struct cpp_device *cpp_dev;

};



struct msm_cpp_payload_params {

	uint32_t stripe_base;

	uint32_t stripe_size;

	uint32_t plane_base;

	uint32_t plane_size;



	/* offsets for stripe/plane pointers in payload */

	uint32_t rd_pntr_off;

	uint32_t wr_0_pntr_off;

	uint32_t rd_ref_pntr_off;

	uint32_t wr_ref_pntr_off;

	uint32_t wr_0_meta_data_wr_pntr_off;

	uint32_t fe_mmu_pf_ptr_off;

	uint32_t ref_fe_mmu_pf_ptr_off;

	uint32_t we_mmu_pf_ptr_off;

	uint32_t dup_we_mmu_pf_ptr_off;

	uint32_t ref_we_mmu_pf_ptr_off;

};



struct cpp_device {

	struct platform_device *pdev;

	struct msm_sd_subdev msm_sd;
@@ -237,22 +256,9 @@ struct cpp_device { 
	uint32_t num_buffq;

	struct v4l2_subdev *buf_mgr_subdev;



	uint32_t rd_pntr;

	uint32_t wr_0_pntr;

	uint32_t wr_1_pntr;

	uint32_t wr_2_pntr;

	uint32_t wr_3_pntr;

	uint32_t rd_ref_pntr;

	uint32_t wr_ref_pntr;

	uint32_t wr_0_meta_data_wr_pntr;

	uint32_t wr_1_meta_data_wr_pntr;

	uint32_t wr_2_meta_data_wr_pntr;

	uint32_t wr_3_meta_data_wr_pntr;

	uint32_t stripe_base;

	uint32_t stripe_size;

	uint32_t stripe_info_offset;

	uint32_t bus_client;

	uint32_t bus_idx;

	uint32_t bus_master_flag;

	struct msm_cpp_payload_params payload_params;

};

#endif /* __MSM_CPP_H__ */