Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit efeac348 authored by Hareesh Gundu's avatar Hareesh Gundu Committed by Gerrit - the friendly Code Review server
Browse files

ARM: dts: msm: Update GPU clock plan for msmgold 



GPU clock plan changed for new requirement. Updated
same to reflect the clock plan.

TURBO: 550Mhz
NOM: 484.4Mhz
SVS+: 400Mhz
SVS: 270Mhz

Change-Id: I30a25705463762209f80760c76a35c760ec6e777
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
parent bf1f2607

arch/arm/boot/dts/qcom/msmgold-gpu.dtsi

+12 −21
Original line number Diff line number Diff line
@@ -112,51 +112,42 @@ 
			/* TURBO */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <598000000>;

				qcom,gpu-freq = <550000000>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <6>;

				qcom,bus-max = <7>;

			};



			/* NOM+ */

			/* NOM */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <523200000>;

				qcom,bus-freq = <6>;

				qcom,bus-min = <5>;

				qcom,bus-max = <7>;

			};



			/* NOM */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <484800000>;

				qcom,bus-freq = <5>;

				qcom,bus-min = <4>;

				qcom,bus-max = <6>;

				qcom,bus-max = <7>;

			};



			/* SVS+ */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <400000000>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <3>;

				qcom,bus-max = <5>;

				qcom,bus-max = <6>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <270000000>;

				qcom,bus-freq = <3>;

				qcom,bus-min = <1>;

				qcom,bus-max = <3>;

				qcom,bus-min = <3>;

				qcom,bus-max = <5>;

			};



			/* XO */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <19200000>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;