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Commit bf1f2607 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: clock-cpu: Fix overflow in CCI clock rate for 32 bit"

parents ef82b3bd 50060ae8

drivers/clk/msm/clock-cpu-titanium.c

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ 
#define APCS_PLL_TEST_CTL_HI	0x34



#define UPDATE_CHECK_MAX_LOOPS 5000

#define CCI_RATE(rate)		((rate * 10) / 25)

#define CCI_RATE(rate)		(div_u64((rate * 10ULL), 25))

#define PLL_MODE(x)		(*(x)->base + (unsigned long) (x)->mode_reg)



#define GLB_DIAG		0x0b11101c

drivers/clk/msm/clock-generic.c

+2 −2
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -267,7 +267,7 @@ static long __div_round_rate(struct div_data *data, unsigned long rate, 
	rate = max(rate, 1UL);



	min_div = max(data->min_div, 1U);

	max_div = min(data->max_div, (unsigned int) (ULONG_MAX / rate));

	max_div = min(data->max_div, (unsigned int) (ULONG_MAX));



	/*

	 * div values are doubled for half dividers.