Commit 50060ae8 authored Feb 02, 2016 by Taniya Das

clk: msm: clock-cpu: Fix overflow in CCI clock rate for 32 bit



The CCI rate is incorrectly calculated due to an overflow, thus fix the
same for 32 bit compilers, which was causing cci clock set failures on 32
bit systems.

CRs-Fixed: 971371
Change-Id: I87da3260c7cf7ce789b6920a75ad20ebabbfc092
Signed-off-by: Taniya Das <tdas@codeaurora.org>

parent a632db1c

drivers/clk/msm/clock-cpu-titanium.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -50,7 +50,7 @@
		#define APCS_PLL_TEST_CTL_HI 0x34

		#define UPDATE_CHECK_MAX_LOOPS 5000
		#define CCI_RATE(rate) ((rate * 10) / 25)
		#define CCI_RATE(rate) (div_u64((rate * 10ULL), 25))
		#define PLL_MODE(x) (*(x)->base + (unsigned long) (x)->mode_reg)

		#define GLB_DIAG 0x0b11101c