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Commit a632db1c authored by Taniya Das's avatar Taniya Das
Browse files

clk: msm: clock-generic: Fix max_div calculation for 32 bit 



The ULONG_MAX value on 32 bit compilers is +4,294,967,295 and when divided
with some high frequencies, it could lead to min_div > max_div. Thus
resulting in clk_set_rate failure for higher frequencies.

CRs-Fixed: 971371
Change-Id: Id982328aeadf24d29e295e042a57453ea4e35c1b
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 8562c3ab

drivers/clk/msm/clock-generic.c

+2 −2
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -267,7 +267,7 @@ static long __div_round_rate(struct div_data *data, unsigned long rate, 
	rate = max(rate, 1UL);



	min_div = max(data->min_div, 1U);

	max_div = min(data->max_div, (unsigned int) (ULONG_MAX / rate));

	max_div = min(data->max_div, (unsigned int) (ULONG_MAX));



	/*

	 * div values are doubled for half dividers.