Merge "clk: msm: clock-gcc-8953: Add support to read efuse for Venus" (e7790a0d) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/clk/msm/clock-gcc-8953.c

+45 −1

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
		* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -412,6 +412,17 @@ static struct clk_freq_tbl ftbl_vcodec0_clk_src[] = {
		F_END
		};

		static struct clk_freq_tbl ftbl_vcodec0_clk_src_540MHz[] = {
		F( 114290000, gpll0_main_div2, 3.5, 0, 0),
		F( 228570000, gpll0, 3.5, 0, 0),
		F( 310000000, gpll2_vcodec, 3, 0, 0),
		F( 360000000, gpll6, 3, 0, 0),
		F( 400000000, gpll0, 2, 0, 0),
		F( 465000000, gpll2_vcodec, 2, 0, 0),
		F( 540000000, gpll6, 2, 0, 0),
		F_END
		};

		static struct rcg_clk vcodec0_clk_src = {
		.cmd_rcgr_reg = VCODEC0_CMD_RCGR,
		.set_rate = set_rate_mnd,
		@@ -3662,6 +3673,37 @@ static struct clk_lookup msm_clocks_lookup[] = {
		CLK_LIST(gcc_mdss_vsync_clk),
		};

		#define SPEED_BIN 7

		static void override_for_8953(struct platform_device *pdev)
		{
		struct resource *res;
		void __iomem *base;
		u32 config_efuse, bin;

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "efuse");
		if (!res)
		return;

		base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
		if (!base) {
		dev_warn(&pdev->dev,
		"Unable to ioremap efuse reg address. Defaulting to 0.\n");
		return;
		}

		config_efuse = readl_relaxed(base);
		devm_iounmap(&pdev->dev, base);

		bin = (config_efuse >> 8) & 0x7;

		if (bin == SPEED_BIN) {
		vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_540MHz;
		vcodec0_clk_src.c.fmax[VDD_DIG_HIGH] = 540000000;
		}

		dev_info(&pdev->dev, "Venus speed bin: %u\n", bin);
		}

		static int msm_gcc_probe(struct platform_device *pdev)
		{
		@@ -3694,6 +3736,8 @@ static int msm_gcc_probe(struct platform_device *pdev)
		return PTR_ERR(vdd_dig.regulator[0]);
		}

		override_for_8953(pdev);

		/Vote for GPLL0 to turn on. Needed by acpuclock. /
		regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
		regval \|= BIT(0);