Merge "clk: msm: clock-cpu-8996: Add V3 support" (e298d754) · Commits · e / devices / android_kernel_xiaomi_markw

Documentation/devicetree/bindings/arm/msm/clock-cpu-8996.txt

+2 −1

Original line number	Diff line number	Diff line
		@@ -6,7 +6,8 @@ the clocks are scaled and also other HW specific parameters like fmax tables,
		PLL FMAXes etc.

		Required properties:
		- compatible: Must be "qcom,cpu-clock-8996"
		- compatible: Must be either "qcom,cpu-clock-8996" or
		"qcom,cpu-clock-8996-v3"
		- reg: Pairs of physical base addresses and region sizes of
		memory mapped registers.
		- reg-names: Names of the bases for the above registers. Expected

drivers/clk/msm/clock-cpu-8996.c

+33 −11

Original line number	Diff line number	Diff line
		@@ -62,6 +62,7 @@ static char *base_names[] = {
		};

		static void *vbases[NUM_BASES];
		static bool cpu_clocks_v3;

		static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);

		@@ -536,8 +537,10 @@ static int cpu_clk_8996_set_rate(struct clk *c, unsigned long rate)
		if (cpuclk->alt_pll_freqs[i] < rate &&
		cpuclk->alt_pll_freqs[i+1] >= rate)
		alt_pll_rate = cpuclk->alt_pll_freqs[i];
		if (!cpu_clocks_v3)
		mutex_lock(&scm_lmh_lock);
		ret = clk_set_rate(cpuclk->alt_pll, alt_pll_rate);
		if (!cpu_clocks_v3)
		mutex_unlock(&scm_lmh_lock);
		if (ret) {
		pr_err("failed to set rate %lu on alt_pll when setting %lu on %s (%d)\n",
		@@ -558,8 +561,10 @@ static int cpu_clk_8996_set_rate(struct clk *c, unsigned long rate)
		* CPU frequency to ramp up from 384MHz to 550MHz.
		*/
		if (c->rate > 600000000 && rate < 600000000) {
		if (!cpu_clocks_v3)
		mutex_lock(&scm_lmh_lock);
		ret = clk_set_rate(c->parent, c->rate/2);
		if (!cpu_clocks_v3)
		mutex_unlock(&scm_lmh_lock);
		if (ret) {
		pr_err("failed to set rate %lu on %s (%d)\n",
		@@ -568,8 +573,10 @@ static int cpu_clk_8996_set_rate(struct clk *c, unsigned long rate)
		}
		}

		if (!cpu_clocks_v3)
		mutex_lock(&scm_lmh_lock);
		ret = clk_set_rate(c->parent, rate);
		if (!cpu_clocks_v3)
		mutex_unlock(&scm_lmh_lock);
		if (ret) {
		pr_err("failed to set rate %lu on %s (%d)\n",
		@@ -585,8 +592,10 @@ static int cpu_clk_8996_set_rate(struct clk *c, unsigned long rate)
		set_rate_fail:
		/* Restore parent rate if we halved it */
		if (c->rate > 600000000 && rate < 600000000) {
		if (!cpu_clocks_v3)
		mutex_lock(&scm_lmh_lock);
		err_ret = clk_set_rate(c->parent, c->rate);
		if (!cpu_clocks_v3)
		mutex_unlock(&scm_lmh_lock);
		if (err_ret)
		pr_err("failed to restore %s rate to %lu\n",
		@@ -595,8 +604,10 @@ set_rate_fail:

		fail:
		if (cpuclk->alt_pll && (n_alt_freqs > 0)) {
		if (!cpu_clocks_v3)
		mutex_lock(&scm_lmh_lock);
		err_ret = clk_set_rate(cpuclk->alt_pll, alt_pll_prev_rate);
		if (!cpu_clocks_v3)
		mutex_unlock(&scm_lmh_lock);
		if (err_ret)
		pr_err("failed to reset rate to %lu on alt pll after failing to set %lu on %s (%d)\n",
		@@ -1177,6 +1188,7 @@ static int cpu_clock_8996_driver_probe(struct platform_device *pdev)

		static struct of_device_id match_table[] = {
		{ .compatible = "qcom,cpu-clock-8996" },
		{ .compatible = "qcom,cpu-clock-8996-v3" },
		{}
		};

		@@ -1232,7 +1244,17 @@ int __init cpu_clock_8996_early_init(void)
		if (!ofnode)
		return 0;

		pr_info("clock-cpu-8996: configuring cluster clocks\n");
		ofnode = of_find_compatible_node(NULL, NULL,
		"qcom,cpu-clock-8996-v3");
		if (ofnode)
		cpu_clocks_v3 = true;

		pr_info("clock-cpu-8996: configuring clocks for the perf cluster\n");

		if (cpu_clocks_v3) {
		pwrcl_alt_pll.offline_bit_workaround = false;
		perfcl_alt_pll.offline_bit_workaround = false;
		}

		/*
		* We definitely don't want to parse DT here - this is too early and in