Loading drivers/clk/msm/clock-alpha-pll.c +2 −1 Original line number Diff line number Diff line Loading @@ -267,6 +267,7 @@ static void alpha_pll_disable_hwfsm(struct clk *c) /* Disable HW FSM */ mode = readl_relaxed(MODE_REG(pll)); mode &= ~PLL_FSM_ENA_BIT; if (pll->offline_bit_workaround) mode &= ~PLL_OFFLINE_REQ_BIT; writel_relaxed(mode, MODE_REG(pll)); Loading drivers/clk/msm/clock-cpu-8996.c +2 −0 Original line number Diff line number Diff line Loading @@ -192,6 +192,7 @@ static struct alpha_pll_clk perfcl_alt_pll = { .enable_config = 0x9, /* Main and early outputs */ .post_div_config = 0x100, /* Div-2 */ .config_ctl_val = 0x4001051B, .offline_bit_workaround = true, .c = { .always_on = true, .parent = &alpha_xo_ao.c, Loading Loading @@ -253,6 +254,7 @@ static struct alpha_pll_clk pwrcl_alt_pll = { .enable_config = 0x9, /* Main and early outputs */ .post_div_config = 0x100, /* Div-2 */ .config_ctl_val = 0x4001051B, .offline_bit_workaround = true, .c = { .always_on = true, .dbg_name = "pwrcl_alt_pll", Loading include/soc/qcom/clock-alpha-pll.h +8 −0 Original line number Diff line number Diff line Loading @@ -66,6 +66,14 @@ struct alpha_pll_clk { bool slew; bool no_prepared_reconfig; /* * Some chipsets need the offline request bit to be * cleared on a second write to the register, even though * SW wants the bit to be set. Set this flag to indicate * that the workaround is required. */ bool offline_bit_workaround; struct clk c; }; Loading Loading
drivers/clk/msm/clock-alpha-pll.c +2 −1 Original line number Diff line number Diff line Loading @@ -267,6 +267,7 @@ static void alpha_pll_disable_hwfsm(struct clk *c) /* Disable HW FSM */ mode = readl_relaxed(MODE_REG(pll)); mode &= ~PLL_FSM_ENA_BIT; if (pll->offline_bit_workaround) mode &= ~PLL_OFFLINE_REQ_BIT; writel_relaxed(mode, MODE_REG(pll)); Loading
drivers/clk/msm/clock-cpu-8996.c +2 −0 Original line number Diff line number Diff line Loading @@ -192,6 +192,7 @@ static struct alpha_pll_clk perfcl_alt_pll = { .enable_config = 0x9, /* Main and early outputs */ .post_div_config = 0x100, /* Div-2 */ .config_ctl_val = 0x4001051B, .offline_bit_workaround = true, .c = { .always_on = true, .parent = &alpha_xo_ao.c, Loading Loading @@ -253,6 +254,7 @@ static struct alpha_pll_clk pwrcl_alt_pll = { .enable_config = 0x9, /* Main and early outputs */ .post_div_config = 0x100, /* Div-2 */ .config_ctl_val = 0x4001051B, .offline_bit_workaround = true, .c = { .always_on = true, .dbg_name = "pwrcl_alt_pll", Loading
include/soc/qcom/clock-alpha-pll.h +8 −0 Original line number Diff line number Diff line Loading @@ -66,6 +66,14 @@ struct alpha_pll_clk { bool slew; bool no_prepared_reconfig; /* * Some chipsets need the offline request bit to be * cleared on a second write to the register, even though * SW wants the bit to be set. Set this flag to indicate * that the workaround is required. */ bool offline_bit_workaround; struct clk c; }; Loading