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Commit de9a14cb authored by Stephen Boyd's avatar Stephen Boyd Committed by Gerrit - the friendly Code Review server
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arm64: cpu_errata: Add Kryo to Falkor 1003 errata 



The Kryo CPUs are also affected by the Falkor 1003 errata, so
we need to do the same workaround on Kryo CPUs. The MIDR is
slightly more complicated here, where the PART number is not
always the same when looking at all the bits from 15 to 4. Drop
the lower 8 bits and just look at the top 4 to see if it's '2'
and then consider those as Kryo CPUs. This covers all the
combinations without having to list them all out.

Change-Id: I076e583462e6b71172e9d7dc282703eb8a52499d
Fixes: 38fd94b0275c ("arm64: Work around Falkor erratum 1003")
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Git-commit: bb48711800e6d7aedbf4dfd3367e0ab1270a6bea
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux


[neeraju@codeaurora.org: resolve merge conflicts.
 Take only the Kryo MIDR definition part.]
Signed-off-by: default avatarNeeraj Upadhyay <neeraju@codeaurora.org>
parent b6a70920

arch/arm64/include/asm/cputype.h

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ 
#define ARM_CPU_PART_CORTEX_A72		0xD08

#define ARM_CPU_PART_KRYO2XX_GOLD	0x800

#define ARM_CPU_PART_KRYO2XX_SILVER	0x801

#define QCOM_CPU_PART_KRYO		0x200



#define APM_CPU_PART_POTENZA	0x000

arch/arm64/kernel/cpu_errata.c

+13 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_KRYO2XX_SILVER MIDR_CPU_PART(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER)

#define MIDR_QCOM_KRYO MIDR_CPU_PART(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)



#define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \

			MIDR_ARCHITECTURE_MASK)
@@ -41,6 +42,18 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry) 
	return (midr >= entry->midr_range_min && midr <= entry->midr_range_max);

}



static bool __maybe_unused

is_kryo_midr(const struct arm64_cpu_capabilities *entry)

{

	u32 model;



	model = read_cpuid_id();

	model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |

		 MIDR_ARCHITECTURE_MASK;



	return model == entry->midr_model;

}



#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

#include <asm/mmu_context.h>

#include <asm/cacheflush.h>