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Commit b6a70920 authored by Will Deacon's avatar Will Deacon Committed by Gerrit - the friendly Code Review server
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arm64: Implement branch predictor hardening for affected Cortex-A CPUs 



Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing
and can theoretically be attacked by malicious code.

This patch implements a PSCI-based mitigation for these CPUs when available.
The call into firmware will invalidate the branch predictor state, preventing
any malicious entries from affecting other victim contexts.

Change-Id: I08acb4a1436709aee7e57ad5e14b37f1a8738038
Co-developed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Git-commit: aa6acde65e03186b5add8151e1ffe36c3c62639b
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux


[neeraju@codeaurora.org: resolve merge conflicts.
 Implement PSCI-based mitigation only for Cortex-A57]
Signed-off-by: default avatarNeeraj Upadhyay <neeraju@codeaurora.org>
parent 0b8d0eb5

arch/arm64/kernel/bpi.S

+24 −0
Original line number Diff line number Diff line
@@ -53,3 +53,27 @@ ENTRY(__bp_harden_hyp_vecs_start) 
	vectors __kvm_hyp_vector

	.endr

ENTRY(__bp_harden_hyp_vecs_end)

ENTRY(__psci_hyp_bp_inval_start)

	sub	sp, sp, #(8 * 18)

	stp	x16, x17, [sp, #(16 * 0)]

	stp	x14, x15, [sp, #(16 * 1)]

	stp	x12, x13, [sp, #(16 * 2)]

	stp	x10, x11, [sp, #(16 * 3)]

	stp	x8, x9, [sp, #(16 * 4)]

	stp	x6, x7, [sp, #(16 * 5)]

	stp	x4, x5, [sp, #(16 * 6)]

	stp	x2, x3, [sp, #(16 * 7)]

	stp	x0, x1, [sp, #(16 * 8)]

	mov	x0, #0x84000000

	smc	#0

	ldp	x16, x17, [sp, #(16 * 0)]

	ldp	x14, x15, [sp, #(16 * 1)]

	ldp	x12, x13, [sp, #(16 * 2)]

	ldp	x10, x11, [sp, #(16 * 3)]

	ldp	x8, x9, [sp, #(16 * 4)]

	ldp	x6, x7, [sp, #(16 * 5)]

	ldp	x4, x5, [sp, #(16 * 6)]

	ldp	x2, x3, [sp, #(16 * 7)]

	ldp	x0, x1, [sp, #(16 * 8)]

	add	sp, sp, #(8 * 18)

ENTRY(__psci_hyp_bp_inval_end)

arch/arm64/kernel/cpu_errata.c

+29 −4
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry) 
DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);



#ifdef CONFIG_KVM

extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[];



static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,

				const char *hyp_vecs_end)

{
@@ -89,8 +91,10 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, 
	spin_unlock(&bp_lock);

}

#else

static void __maybe_unused

__install_bp_hardening_cb(bp_hardening_cb_t fn,

#define __psci_hyp_bp_inval_start	NULL

#define __psci_hyp_bp_inval_end		NULL



static void __install_bp_hardening_cb(bp_hardening_cb_t fn,

				      const char *hyp_vecs_start,

				      const char *hyp_vecs_end)

{
@@ -115,6 +119,20 @@ install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, 


	__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);

}



#include <asm/psci.h>



static void enable_psci_bp_hardening(void *data)

{

	const struct arm64_cpu_capabilities *entry = data;



	if (psci_ops.get_version)

		install_bp_hardening_cb(entry,

				       (bp_hardening_cb_t)psci_ops.get_version,

				       __psci_hyp_bp_inval_start,

				       __psci_hyp_bp_inval_end);



}

#endif	/* CONFIG_HARDEN_BRANCH_PREDICTOR */



#define MIDR_RANGE(model, min, max) \
@@ -170,6 +188,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.capability = ARM64_WORKAROUND_845719,

		MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA00004, 0xA00004),

	},

#endif

#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),

		.enable = enable_psci_bp_hardening,

	},

#endif

	{

	}