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Commit dadd43ff authored by Marcus Weseloh's avatar Marcus Weseloh Committed by Sasha Levin
Browse files

spi: sun4i: allow transfers to set transmission speed 



[ Upstream commit 47284e3e0f3c427c93f8583549b6c938e8a18015 ]

Allow transfers to set the transmission speed rather than using the
device max_speed_hz value. The SPI core makes sure that the speed_hz
value is always set on the transfer.

Signed-off-by: default avatarMarcus Weseloh <mweseloh42@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent ab50dd9e

drivers/spi/spi-sun4i.c

+4 −4
Original line number Diff line number Diff line
@@ -232,8 +232,8 @@ static int sun4i_spi_transfer_one(struct spi_master *master, 


	/* Ensure that we have a parent clock fast enough */

	mclk_rate = clk_get_rate(sspi->mclk);

	if (mclk_rate < (2 * spi->max_speed_hz)) {

		clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);

	if (mclk_rate < (2 * tfr->speed_hz)) {

		clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);

		mclk_rate = clk_get_rate(sspi->mclk);

	}
@@ -251,14 +251,14 @@ static int sun4i_spi_transfer_one(struct spi_master *master, 
	 * First try CDR2, and if we can't reach the expected

	 * frequency, fall back to CDR1.

	 */

	div = mclk_rate / (2 * spi->max_speed_hz);

	div = mclk_rate / (2 * tfr->speed_hz);

	if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {

		if (div > 0)

			div--;



		reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;

	} else {

		div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);

		div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);

		reg = SUN4I_CLK_CTL_CDR1(div);

	}

drivers/spi/spi-sun6i.c

+4 −4
Original line number Diff line number Diff line
@@ -217,8 +217,8 @@ static int sun6i_spi_transfer_one(struct spi_master *master, 


	/* Ensure that we have a parent clock fast enough */

	mclk_rate = clk_get_rate(sspi->mclk);

	if (mclk_rate < (2 * spi->max_speed_hz)) {

		clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);

	if (mclk_rate < (2 * tfr->speed_hz)) {

		clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);

		mclk_rate = clk_get_rate(sspi->mclk);

	}
@@ -236,14 +236,14 @@ static int sun6i_spi_transfer_one(struct spi_master *master, 
	 * First try CDR2, and if we can't reach the expected

	 * frequency, fall back to CDR1.

	 */

	div = mclk_rate / (2 * spi->max_speed_hz);

	div = mclk_rate / (2 * tfr->speed_hz);

	if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {

		if (div > 0)

			div--;



		reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;

	} else {

		div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);

		div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);

		reg = SUN6I_CLK_CTL_CDR1(div);

	}