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Commit ab50dd9e authored by Michal Suchanek's avatar Michal Suchanek Committed by Sasha Levin
Browse files

spi: sun4i: fix FIFO limit 



[ Upstream commit 6d9fe44bd73d567d04d3a68a2d2fa521ab9532f2 ]

When testing SPI without DMA I noticed that filling the FIFO on the
spi controller causes timeout.

Always leave room for one byte in the FIFO.

Signed-off-by: default avatarMichal Suchanek <hramrach@gmail.com>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent d259ae2b

drivers/spi/spi-sun4i.c

+10 −3
Original line number Diff line number Diff line
@@ -176,7 +176,10 @@ static int sun4i_spi_transfer_one(struct spi_master *master, 


	/* We don't support transfer larger than the FIFO */

	if (tfr->len > SUN4I_FIFO_DEPTH)

		return -EINVAL;

		return -EMSGSIZE;



	if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH)

		return -EMSGSIZE;



	reinit_completion(&sspi->done);

	sspi->tx_buf = tfr->tx_buf;
@@ -269,8 +272,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master, 
	sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));

	sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));



	/* Fill the TX FIFO */

	sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);

	/*

	 * Fill the TX FIFO

	 * Filling the FIFO fully causes timeout for some reason

	 * at least on spi2 on A10s

	 */

	sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);



	/* Enable the interrupts */

	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);