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Commit d511026a authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add support for clock cpu for MSMtitanium 



CPU clock node will enable the real cpu clocks which will be required to
enable cpu scaling for the cluster/cci.

Change-Id: Ie14d99b7e14fb3067e94ee8ac6cf9b2faadaf031
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent d5c2948f

arch/arm/boot/dts/qcom/msmtitanium-rumi.dts

+4 −0
Original line number Diff line number Diff line
@@ -108,3 +108,7 @@ 
&pmtitanium_adc_tm {

	status = "disabled";

};



&clock_cpu {

	compatible = "qcom,dummycc";

};

arch/arm/boot/dts/qcom/msmtitanium.dtsi

+40 −0
Original line number Diff line number Diff line
@@ -708,6 +708,46 @@ 
		#clock-cells = <1>;

	};



	clock_cpu: qcom,cpu-clock-titanium@b116000 {

		compatible = "qcom,cpu-clock-titanium";

		reg =   <0xb114000  0x68>,

			<0xb014000  0x68>,

			<0xb116000  0x400>,

			<0xb111050  0x08>,

			<0xb011050  0x08>,

			<0xb1d1050  0x08>,

			<0x00a4124  0x08>;

		reg-names = "rcgwr-c0-base", "rcgwr-c1-base",

			    "c0-pll", "c0-mux", "c1-mux",

			    "cci-mux", "efuse";

		vdd-mx-supply = <&pmtitanium_s7_level_ao>;

		vdd-cl-supply = <&apc_vreg>;

		clocks = <&clock_gcc clk_xo_a_clk_src>;

		clock-names = "xo_a";

		qcom,num-clusters = <2>;

		qcom,speed0-bin-v0-cl =

			<          0 0>,

			<  652800000 1>,

			< 1036800000 2>,

			< 1401600000 3>,

			< 1689600000 4>,

			< 1843200000 5>,

			< 1958400000 6>,

			< 2150400000 7>,

			< 2208000000 8>;

		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  307200000 1>,

			<  414720000 2>,

			<  560640000 3>,

			<  675840000 4>,

			<  737280000 5>,

			<  783360000 6>,

			<  860160000 7>,

			<  883200000 8>;

		#clock-cells = <1>;

	};



	rpm_bus: qcom,rpm-smd {

		compatible = "qcom,rpm-smd";

		rpm-channel-name = "rpm_requests";