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Commit d4599eea authored by Amir Levy's avatar Amir Levy
Browse files

msm: ipa3: assign resources limitation to each group 



Configure IPA source and destination Resource Group registers.
assign limitation for each resource-type and resource group according to
the architecture document.

Change-Id: I0f9b97bfd416d86cc3703eac5ae3330c3f8a70df
Signed-off-by: default avatarNadine Toledano <nadinet@codeaurora.org>
Signed-off-by: default avatarAmir Levy <alevy@codeaurora.org>
parent 6a5a3440

drivers/platform/msm/ipa/ipa_v3/ipa.c

+3 −0
Original line number Diff line number Diff line
@@ -3230,6 +3230,9 @@ static int ipa3_init(const struct ipa3_plat_drv_res *resource_p, 
	spin_lock_init(&ipa3_ctx->ipa3_active_clients.spinlock);

	ipa3_ctx->ipa3_active_clients.cnt = 1;



	/* Assign resource limitation to each group */

	ipa3_set_resorce_groups_min_max_limits();



	/* Create workqueues for power management */

	ipa3_ctx->power_mgmt_wq =

		create_singlethread_workqueue("ipa_power_mgmt");

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

+1 −0
Original line number Diff line number Diff line
@@ -2021,5 +2021,6 @@ int ipa3_release_wdi_mapping(u32 num_buffers, struct ipa_wdi_buffer_info *info); 
int ipa3_create_wdi_mapping(u32 num_buffers, struct ipa_wdi_buffer_info *info);

int ipa3_set_flt_tuple_mask(int pipe_idx, struct ipa3_hash_tuple *tuple);

int ipa3_set_rt_tuple_mask(int tbl_idx, struct ipa3_hash_tuple *tuple);

void ipa3_set_resorce_groups_min_max_limits(void);



#endif /* _IPA3_I_H_ */

drivers/platform/msm/ipa/ipa_v3/ipa_reg.h

+15 −8
Original line number Diff line number Diff line
@@ -219,14 +219,21 @@ 
#define IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n(n) (0x00000404 + 0x20 * (n))

#define IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n(n) (0x00000408 + 0x20 * (n))

#define IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n(n) (0x0000040C + 0x20 * (n))

#define IPA_SRC_RSRC_GRP_XY_RSRC_TYPE_n_SRC_RSRC_GRP_Y_MAX_LIMIT_BMSK 0xFF000000

#define IPA_SRC_RSRC_GRP_XY_RSRC_TYPE_n_SRC_RSRC_GRP_Y_MAX_LIMIT_SHFT 24

#define IPA_SRC_RSRC_GRP_XY_RSRC_TYPE_n_SRC_RSRC_GRP_Y_MIN_LIMIT_BMSK 0xFF0000

#define IPA_SRC_RSRC_GRP_XY_RSRC_TYPE_n_SRC_RSRC_GRP_Y_MIN_LIMIT_SHFT 16

#define IPA_SRC_RSRC_GRP_XY_RSRC_TYPE_n_SRC_RSRC_GRP_X_MAX_LIMIT_BMSK 0xFF00

#define IPA_SRC_RSRC_GRP_XY_RSRC_TYPE_n_SRC_RSRC_GRP_X_MAX_LIMIT_SHFT 8

#define IPA_SRC_RSRC_GRP_XY_RSRC_TYPE_n_SRC_RSRC_GRP_X_MIN_LIMIT_BMSK 0xFF

#define IPA_SRC_RSRC_GRP_XY_RSRC_TYPE_n_SRC_RSRC_GRP_X_MIN_LIMIT_SHFT 0





#define IPA_DST_RSRC_GRP_01_RSRC_TYPE_n(n) (0x00000500 + 0x20 * (n))

#define IPA_DST_RSRC_GRP_23_RSRC_TYPE_n(n) (0x00000504 + 0x20 * (n))

#define IPA_DST_RSRC_GRP_45_RSRC_TYPE_n(n) (0x00000508 + 0x20 * (n))

#define IPA_DST_RSRC_GRP_67_RSRC_TYPE_n(n) (0x0000050c + 0x20 * (n))



#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK 0xFF000000

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT 24

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK 0xFF0000

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT 16

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK 0xFF00

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT 8

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK 0xFF

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT 0



#define IPA_IRQ_EE_UC_n_OFFS(n) (0x0000301c + 0x1000 * (n))

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+180 −10
Original line number Diff line number Diff line
@@ -50,16 +50,6 @@ 
 */

#define IPA_SPARE_REG_1_VAL (0x0000001D)



#define IPA_GROUP_UL      (0)

#define IPA_GROUP_DL      (1)

#define IPA_GROUP_Q6ZIP   (2)

#define IPA_GROUP_DPL     (3)

#define IPA_GROUP_DIAG    IPA_GROUP_DPL

#define IPA_GROUP_DMA     (4)

#define IPA_GROUP_IMM_CMD  IPA_GROUP_DMA

#define IPA_GROUP_UC_RX_Q (5)

#define IPA_CLIENT_NOT_USED {-1, -1, false}





/* HPS, DPS sequencers Types*/

#define IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY  0x00000000
@@ -80,6 +70,74 @@ 
/* COMP/DECOMP */

#define IPA_DPS_HPS_SEQ_TYPE_DMA_COMP_DECOMP 0x00000020



#define IPA_CLIENT_NOT_USED {-1, -1, false}



/* Resource Group index*/

#define IPA_GROUP_UL		(0)

#define IPA_GROUP_DL		(1)

#define IPA_GROUP_DIAG		(2)

#define IPA_GROUP_DPL		IPA_GROUP_DIAG

#define IPA_GROUP_DMA		(3)

#define IPA_GROUP_IMM_CMD	IPA_GROUP_DMA

#define IPA_GROUP_Q6ZIP		(4)

#define IPA_GROUP_Q6ZIP_GENERAL	IPA_GROUP_Q6ZIP

#define IPA_GROUP_UC_RX_Q	(5)

#define IPA_GROUP_Q6ZIP_ENGINE	IPA_GROUP_UC_RX_Q

#define IPA_GROUP_MAX		(6)



enum ipa_rsrc_grp_type_src {

	IPA_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS,

	IPA_RSRC_GRP_TYPE_SRC_HDR_SECTORS,

	IPA_RSRC_GRP_TYPE_SRC_HDRI1_BUFFER,

	IPA_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS,

	IPA_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF,

	IPA_RSRC_GRP_TYPE_SRC_HDRI2_BUFFERS,

	IPA_RSRC_GRP_TYPE_SRC_HPS_DMARS,

	IPA_RSRC_GRP_TYPE_SRC_ACK_ENTRIES,

	IPA_RSRC_GRP_TYPE_SRC_MAX,

};

enum ipa_rsrc_grp_type_dst {

	IPA_RSRC_GRP_TYPE_DST_DATA_SECTORS,

	IPA_RSRC_GRP_TYPE_DST_DATA_SECTOR_LISTS,

	IPA_RSRC_GRP_TYPE_DST_DPS_DMARS,

	IPA_RSRC_GRP_TYPE_DST_MAX,

};



struct rsrc_min_max {

	u32 min;

	u32 max;

};



static const struct rsrc_min_max ipa3_rsrc_src_grp_config

			[IPA_RSRC_GRP_TYPE_SRC_MAX][IPA_GROUP_MAX] = {

		/*UL	DL	DIAG	DMA	Q6zip	uC Rx*/

	[IPA_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{3, 255}, {3, 255}, {1, 255}, {1, 255}, {3, 255}, {1, 255} },

	[IPA_RSRC_GRP_TYPE_SRC_HDR_SECTORS] = {

		{0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255} },

	[IPA_RSRC_GRP_TYPE_SRC_HDRI1_BUFFER] = {

		{0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255} },

	[IPA_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {

		{12, 12}, {12, 12}, {5, 5}, {5, 5},  {8, 8}, {6, 6} },

	[IPA_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {

		{19, 19}, {20, 20}, {5, 5}, {5, 5}, {8, 8}, {6, 6} },

	[IPA_RSRC_GRP_TYPE_SRC_HDRI2_BUFFERS] = {

		{0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255} },

	[IPA_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {

		{1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1} },

	[IPA_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {

		{12, 12},   {12, 12}, {5, 5}, {5, 5}, {8, 8}, {6, 6} },

};

static const struct rsrc_min_max ipa3_rsrc_dst_grp_config

			[IPA_RSRC_GRP_TYPE_DST_MAX][IPA_GROUP_MAX] = {

		/*UL	DL	DIAG	DMA  Q6zip_gen Q6zip_eng*/

	[IPA_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {

		{3, 3}, {3, 3}, {1, 1}, {2, 2}, {2, 2}, {2, 2} },

	[IPA_RSRC_GRP_TYPE_DST_DATA_SECTOR_LISTS] = {

		{0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 255} },

	[IPA_RSRC_GRP_TYPE_DST_DPS_DMARS] = {

		{1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {0, 0} },

};



static const int ipa_ofst_meq32[] = { IPA_OFFSET_MEQ32_0,

					IPA_OFFSET_MEQ32_1, -1 };
@@ -4622,3 +4680,115 @@ bool ipa_is_modem_pipe(int pipe_idx) 


	return false;

}



static void ipa3_write_rsrc_grp_type_reg(int group_index,

			enum ipa_rsrc_grp_type_src n, bool src, u32 val) {



	if (src) {

		switch (group_index) {

		case IPA_GROUP_UL:

		case IPA_GROUP_DL:

			ipa_write_reg(ipa3_ctx->mmio,

				IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n(n), val);

			break;

		case IPA_GROUP_DIAG:

		case IPA_GROUP_DMA:

			ipa_write_reg(ipa3_ctx->mmio,

				IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n(n), val);

			break;

		case IPA_GROUP_Q6ZIP:

		case IPA_GROUP_UC_RX_Q:

			ipa_write_reg(ipa3_ctx->mmio,

				IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n(n), val);

			break;

		default:

			IPAERR(

			" Invalid source resource group,index #%d\n",

			group_index);

			break;

		}

	} else {

		switch (group_index) {

		case IPA_GROUP_UL:

		case IPA_GROUP_DL:

			ipa_write_reg(ipa3_ctx->mmio,

				IPA_DST_RSRC_GRP_01_RSRC_TYPE_n(n), val);

			break;

		case IPA_GROUP_DIAG:

		case IPA_GROUP_DMA:

			ipa_write_reg(ipa3_ctx->mmio,

				IPA_DST_RSRC_GRP_23_RSRC_TYPE_n(n), val);

			break;

		case IPA_GROUP_Q6ZIP_GENERAL:

		case IPA_GROUP_Q6ZIP_ENGINE:

			ipa_write_reg(ipa3_ctx->mmio,

				IPA_DST_RSRC_GRP_45_RSRC_TYPE_n(n), val);

			break;

		default:

			IPAERR(

			" Invalid destination resource group,index #%d\n",

			group_index);

			break;

		}

	}

}



void ipa3_set_resorce_groups_min_max_limits(void)

{

	int i;

	int j;

	u32 reg;



	IPADBG("ENTER\n");

	IPADBG("Assign source rsrc groups min-max limits\n");



	for (i = 0; i < IPA_RSRC_GRP_TYPE_SRC_MAX; i++) {

		for (j = 0; j < IPA_GROUP_MAX; j = j + 2) {

			reg = 0;

			IPA_SETFIELD_IN_REG(reg,

				ipa3_rsrc_src_grp_config[i][j].min,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK);

			IPA_SETFIELD_IN_REG(reg,

				ipa3_rsrc_src_grp_config[i][j].max,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK);

			IPA_SETFIELD_IN_REG(reg,

				ipa3_rsrc_src_grp_config[i][j + 1].min,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK);

			IPA_SETFIELD_IN_REG(reg,

				ipa3_rsrc_src_grp_config[i][j + 1].max,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK);

			ipa3_write_rsrc_grp_type_reg(j, i, true, reg);

		}

	}



	IPADBG("Assign destination rsrc groups min-max limits\n");



	for (i = 0; i < IPA_RSRC_GRP_TYPE_DST_MAX; i++) {

		for (j = 0; j < IPA_GROUP_MAX; j = j + 2) {

			reg = 0;

			IPA_SETFIELD_IN_REG(reg,

				ipa3_rsrc_dst_grp_config[i][j].min,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK);

			IPA_SETFIELD_IN_REG(reg,

				ipa3_rsrc_dst_grp_config[i][j].max,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK);

			IPA_SETFIELD_IN_REG(reg,

				ipa3_rsrc_dst_grp_config[i][j + 1].min,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK);

			IPA_SETFIELD_IN_REG(reg,

				ipa3_rsrc_dst_grp_config[i][j + 1].max,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT,

				IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK);

			ipa3_write_rsrc_grp_type_reg(j, i, false, reg);

		}

	}



	IPADBG("EXIT\n");

}