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Commit 6a5a3440 authored by Amir Levy's avatar Amir Levy
Browse files

msm: ipa3: configure sequencers type



In order to connect endpoints in DMA mode we
need to configure HPS, DPS sequancers to DMA sequence.
This change set IPA_ENDP_INIT_SEQ_n register to DMA only
in case of ep_mode = DMA  and to Packet Processing, no decipher,
uCP in case of basic mode.

Change-Id: Ie685cffa72d3a96eb8dbc94e15d8072936697056
Signed-off-by: default avatarNadine Toledano <nadinet@codeaurora.org>
Signed-off-by: default avatarAmir Levy <alevy@codeaurora.org>
parent 70c709e2
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+10 −0
Original line number Original line Diff line number Diff line
@@ -271,4 +271,14 @@
#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_SHFT 22
#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_SHFT 22
#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_BMSK 0x400000
#define IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_BMSK 0x400000


#define IPA_ENDP_INIT_SEQ_n_OFST(n) (0x0000083C + 0x70*(n))
#define IPA_ENDP_INIT_SEQ_n_DPS_REP_SEQ_TYPE_BMSK 0xf000
#define IPA_ENDP_INIT_SEQ_n_DPS_REP_SEQ_TYPE_SHFT 0xc
#define IPA_ENDP_INIT_SEQ_n_HPS_REP_SEQ_TYPE_BMSK 0xf00
#define IPA_ENDP_INIT_SEQ_n_HPS_REP_SEQ_TYPE_SHFT 0x8
#define IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_BMSK 0xf0
#define IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_SHFT 0x4
#define IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_BMSK 0xf
#define IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_SHFT 0x0

#endif
#endif
+31 −0
Original line number Original line Diff line number Diff line
@@ -60,6 +60,27 @@
#define IPA_GROUP_UC_RX_Q (5)
#define IPA_GROUP_UC_RX_Q (5)
#define IPA_CLIENT_NOT_USED {-1, -1, false}
#define IPA_CLIENT_NOT_USED {-1, -1, false}



/* HPS, DPS sequencers Types*/
#define IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY  0x00000000
/* DMA + DECIPHER/CIPHER */
#define IPA_DPS_HPS_SEQ_TYPE_DMA_DEC 0x00000011
/* Packet Processing + no decipher + uCP (for Ethernet Bridging) */
#define IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP 0x00000002
/* Packet Processing + decipher + uCP */
#define IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_DEC_UCP 0x00000013
/* 2 Packet Processing pass + no decipher + uCP */
#define IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP 0x00000004
/* 2 Packet Processing pass + decipher + uCP */
#define IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP 0x00000015
/* Packet Processing + no decipher + no uCP */
#define IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_NO_UCP 0x00000006
/* Packet Processing + no decipher + no uCP */
#define IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_DEC_NO_UCP 0x00000017
/* COMP/DECOMP */
#define IPA_DPS_HPS_SEQ_TYPE_DMA_COMP_DECOMP 0x00000020


static const int ipa_ofst_meq32[] = { IPA_OFFSET_MEQ32_0,
static const int ipa_ofst_meq32[] = { IPA_OFFSET_MEQ32_0,
					IPA_OFFSET_MEQ32_1, -1 };
					IPA_OFFSET_MEQ32_1, -1 };
static const int ipa_ofst_meq128[] = { IPA_OFFSET_MEQ128_0,
static const int ipa_ofst_meq128[] = { IPA_OFFSET_MEQ128_0,
@@ -2932,6 +2953,7 @@ void _ipa_cfg_ep_mode_v3_0(u32 pipe_number, u32 dst_pipe_number,
int ipa3_cfg_ep_mode(u32 clnt_hdl, const struct ipa_ep_cfg_mode *ep_mode)
int ipa3_cfg_ep_mode(u32 clnt_hdl, const struct ipa_ep_cfg_mode *ep_mode)
{
{
	int ep;
	int ep;
	int type;


	if (clnt_hdl >= ipa3_ctx->ipa_num_pipes ||
	if (clnt_hdl >= ipa3_ctx->ipa_num_pipes ||
	    ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_mode == NULL) {
	    ipa3_ctx->ep[clnt_hdl].valid == 0 || ep_mode == NULL) {
@@ -2972,6 +2994,15 @@ int ipa3_cfg_ep_mode(u32 clnt_hdl, const struct ipa_ep_cfg_mode *ep_mode)
			ipa3_ctx->ep[clnt_hdl].dst_pipe_index,
			ipa3_ctx->ep[clnt_hdl].dst_pipe_index,
			ep_mode);
			ep_mode);


	 /* Configure sequencers type*/
	if (ep_mode->mode == IPA_DMA)
		type = IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY;
	else
		type = IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP;

	IPADBG(" set sequencers to sequance 0x%x, ep = %d\n", type, clnt_hdl);
	ipa_write_reg(ipa3_ctx->mmio, IPA_ENDP_INIT_SEQ_n_OFST(clnt_hdl), type);

	ipa3_dec_client_disable_clks();
	ipa3_dec_client_disable_clks();


	return 0;
	return 0;