Loading drivers/gpu/msm/adreno_a3xx.c +9 −0 Original line number Diff line number Diff line Loading @@ -1320,6 +1320,15 @@ static void a3xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, A3XX_RBBM_PERFCTR_CTL, 0x01); kgsl_regwrite(device, A3XX_CP_DEBUG, A3XX_CP_DEBUG_DEFAULT); /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */ if (adreno_is_a305b(adreno_dev) || adreno_is_a310(adreno_dev) || adreno_is_a330(adreno_dev)) kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x003E2008); else kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x000E0602); } static struct adreno_coresight_register a3xx_coresight_registers[] = { Loading drivers/gpu/msm/adreno_ringbuffer.c +0 −11 Original line number Diff line number Diff line Loading @@ -301,17 +301,6 @@ static void _ringbuffer_setup_common(struct adreno_device *adreno_dev) adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_BASE, ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc.gpuaddr); /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */ if (adreno_is_a3xx(adreno_dev)) { unsigned int val = 0x000E0602; if (adreno_is_a305b(adreno_dev) || adreno_is_a310(adreno_dev) || adreno_is_a330(adreno_dev)) val = 0x003E2008; kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, val); } } /** Loading Loading
drivers/gpu/msm/adreno_a3xx.c +9 −0 Original line number Diff line number Diff line Loading @@ -1320,6 +1320,15 @@ static void a3xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, A3XX_RBBM_PERFCTR_CTL, 0x01); kgsl_regwrite(device, A3XX_CP_DEBUG, A3XX_CP_DEBUG_DEFAULT); /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */ if (adreno_is_a305b(adreno_dev) || adreno_is_a310(adreno_dev) || adreno_is_a330(adreno_dev)) kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x003E2008); else kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x000E0602); } static struct adreno_coresight_register a3xx_coresight_registers[] = { Loading
drivers/gpu/msm/adreno_ringbuffer.c +0 −11 Original line number Diff line number Diff line Loading @@ -301,17 +301,6 @@ static void _ringbuffer_setup_common(struct adreno_device *adreno_dev) adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_BASE, ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc.gpuaddr); /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */ if (adreno_is_a3xx(adreno_dev)) { unsigned int val = 0x000E0602; if (adreno_is_a305b(adreno_dev) || adreno_is_a310(adreno_dev) || adreno_is_a330(adreno_dev)) val = 0x003E2008; kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, val); } } /** Loading