Loading drivers/gpu/msm/adreno.h +1 −3 Original line number Diff line number Diff line Loading @@ -33,8 +33,6 @@ #define DEVICE_3D_NAME "kgsl-3d" #define DEVICE_3D0_NAME "kgsl-3d0" #define ADRENO_PRIORITY_MAX_RB_LEVELS 4 /* ADRENO_DEVICE - Given a kgsl_device return the adreno device struct */ #define ADRENO_DEVICE(device) \ container_of(device, struct adreno_device, dev) Loading Loading @@ -339,7 +337,7 @@ struct adreno_device { struct kgsl_memdesc pm4; size_t gpmu_cmds_size; unsigned int *gpmu_cmds; struct adreno_ringbuffer ringbuffers[ADRENO_PRIORITY_MAX_RB_LEVELS]; struct adreno_ringbuffer ringbuffers[KGSL_PRIORITY_MAX_RB_LEVELS]; int num_ringbuffers; struct adreno_ringbuffer *cur_rb; struct adreno_ringbuffer *next_rb; Loading drivers/gpu/msm/adreno_a4xx.c +1 −1 Original line number Diff line number Diff line Loading @@ -2233,7 +2233,7 @@ struct adreno_gpudev adreno_a4xx_gpudev = { .irq = &a4xx_irq, .irq_trace = trace_kgsl_a4xx_irq_status, .snapshot_data = &a4xx_snapshot_data, .num_prio_levels = ADRENO_PRIORITY_MAX_RB_LEVELS, .num_prio_levels = KGSL_PRIORITY_MAX_RB_LEVELS, .vbif_xin_halt_ctrl0_mask = A4XX_VBIF_XIN_HALT_CTRL0_MASK, .perfcounter_init = a4xx_perfcounter_init, Loading drivers/gpu/msm/adreno_a5xx.c +1 −1 Original line number Diff line number Diff line Loading @@ -3912,7 +3912,7 @@ struct adreno_gpudev adreno_a5xx_gpudev = { .irq = &a5xx_irq, .snapshot_data = &a5xx_snapshot_data, .irq_trace = trace_kgsl_a5xx_irq_status, .num_prio_levels = ADRENO_PRIORITY_MAX_RB_LEVELS, .num_prio_levels = KGSL_PRIORITY_MAX_RB_LEVELS, .platform_setup = a5xx_platform_setup, .init = a5xx_init, .rb_init = a5xx_rb_init, Loading Loading
drivers/gpu/msm/adreno.h +1 −3 Original line number Diff line number Diff line Loading @@ -33,8 +33,6 @@ #define DEVICE_3D_NAME "kgsl-3d" #define DEVICE_3D0_NAME "kgsl-3d0" #define ADRENO_PRIORITY_MAX_RB_LEVELS 4 /* ADRENO_DEVICE - Given a kgsl_device return the adreno device struct */ #define ADRENO_DEVICE(device) \ container_of(device, struct adreno_device, dev) Loading Loading @@ -339,7 +337,7 @@ struct adreno_device { struct kgsl_memdesc pm4; size_t gpmu_cmds_size; unsigned int *gpmu_cmds; struct adreno_ringbuffer ringbuffers[ADRENO_PRIORITY_MAX_RB_LEVELS]; struct adreno_ringbuffer ringbuffers[KGSL_PRIORITY_MAX_RB_LEVELS]; int num_ringbuffers; struct adreno_ringbuffer *cur_rb; struct adreno_ringbuffer *next_rb; Loading
drivers/gpu/msm/adreno_a4xx.c +1 −1 Original line number Diff line number Diff line Loading @@ -2233,7 +2233,7 @@ struct adreno_gpudev adreno_a4xx_gpudev = { .irq = &a4xx_irq, .irq_trace = trace_kgsl_a4xx_irq_status, .snapshot_data = &a4xx_snapshot_data, .num_prio_levels = ADRENO_PRIORITY_MAX_RB_LEVELS, .num_prio_levels = KGSL_PRIORITY_MAX_RB_LEVELS, .vbif_xin_halt_ctrl0_mask = A4XX_VBIF_XIN_HALT_CTRL0_MASK, .perfcounter_init = a4xx_perfcounter_init, Loading
drivers/gpu/msm/adreno_a5xx.c +1 −1 Original line number Diff line number Diff line Loading @@ -3912,7 +3912,7 @@ struct adreno_gpudev adreno_a5xx_gpudev = { .irq = &a5xx_irq, .snapshot_data = &a5xx_snapshot_data, .irq_trace = trace_kgsl_a5xx_irq_status, .num_prio_levels = ADRENO_PRIORITY_MAX_RB_LEVELS, .num_prio_levels = KGSL_PRIORITY_MAX_RB_LEVELS, .platform_setup = a5xx_platform_setup, .init = a5xx_init, .rb_init = a5xx_rb_init, Loading